Topological insulators, such as single-crystal Bi.sub.2Se.sub.3 nanowires, can be used as the conduction channel in high-performance transistors, a basic circuit building block. Such transistors exhibit current-voltage characteristics superior to semiconductor nanowire transistors, including sharp turn-on, nearly zero cutoff current, very large On/Off current ratio, and well-saturated output current. The metallic electron transport at the surface with good effective mobility can be effectively separated from the conduction of the bulk topological insulator and adjusted by field effect at a small gate voltage. Topological insulators, such as Bi.sub.2Se.sub.3, also have a magneto-electric effect that causes transistor threshold voltage shifts with external magnetic field. These properties are desirable for numerous microelectronic and nanoelectronic circuitry applications, among other applications.

This application concerns quantum computing, and in particular to structures and mechanisms for providing topologically protected quantum computation. In certain embodiments, a magnetic tunnel barrier is controlled that separates Majorona zero modes (“MZMs”) from an edge area (e.g., a gapless edge) of a quantum spin hall system. In particular implementations, the magnetic tunnel barrier is formed from a pair of magnetic insulators whose magnetization is held constant, and the magnetic tunnel barrier is tuned by controlling a gate controlling the electron density around the magnetic insulator in the QSH plane, thereby forming a quantum dot. And, in some implementations, a state of the quantum dot is read out (e.g., using a charge sensor as disclosed herein).

Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, a trench contact formed on and in contact with the source/drain, and a source/drain contact formed on an in contact with the trench contact. A recess is formed in a portion of the source/drain contact using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the source/drain contact. A metallization layer is formed in contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.

A first aspect provides a topological quantum computing device comprising a network of semiconductor-superconductor nanowires, each nanowire comprising a length of semiconductor formed over a substrate and a coating of superconductor formed over at least part of the semiconductor; wherein at least some of the nanowires further comprise a coating of ferromagnetic insulator disposed over at least part of the semiconductor. A second aspect provides a method of fabricating a quantum or spintronic device comprising a heterostructure of semiconductor and ferromagnetic insulator, by: forming a portion of the semiconductor over a substrate in a first vacuum chamber, and growing a coating of the ferromagnetic insulator on the semiconductor by epitaxy in a second vacuum chamber connected to the first vacuum chamber by a vacuum tunnel, wherein the semiconductor comprises InAs and the ferromagnetic insulator comprises EuS.

Disclosed herein is a structure comprising: a gate electrode, a dielectric layer, and a planar layer of a topological material being separated from the gate electrode by at least the dielectric layer, and having a contact interface with the dielectric layer to generate an electric field-controlled Rashba spin-orbit interaction on application of an electric field thereto, wherein the topological material exhibits a topological phase transition between a trivial state and a non-trivial state at a critical electric field strength on application of the electric field, wherein the gate electrode is configured to apply the electric field across the planar layer in a direction perpendicular to a plane of the planar layer; and wherein the topological material exhibits a change in bandgap, in the presence of the electric field, having a spin-dependent contribution represented by a proportionality constant R and a non-spin-dependent contribution represented by a proportionality constant v; and wherein R>.sub.v/3.

Subject matter disclosed herein may relate to programmable current for correlated electron switches.

A non-Boolean analog system includes a first Mott memristor having a first value of a characteristic, and a second Mott memristor having a second value of the characteristic different than the first value. The system includes a resistance in series with the first and second Mott memristors to form a network having a capacitance and that is operable as a relaxation oscillator. Responsive to electrical excitation, a temperature of the network operating an environment including ambient thermal noise settles at an equilibrium corresponding to a global minimum that is a maximally optimal global solution to a global optimization problem to which the network corresponds.

Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.

A first aspect provides a topological quantum computing device comprising a network of semiconductor-superconductor nanowires, each nanowire comprising a length of semiconductor formed over a substrate and a coating of superconductor formed over at least part of the semiconductor; wherein at least some of the nanowires further comprise a coating of ferromagnetic insulator disposed over at least part of the semiconductor. A second aspect provides a method of fabricating a quantum or spintronic device comprising a heterostructure of semiconductor and ferromagnetic insulator, by: forming a portion of the semiconductor over a substrate in a first vacuum chamber, and growing a coating of the ferromagnetic insulator on the semiconductor by epitaxy in a second vacuum chamber connected to the first vacuum chamber by a vacuum tunnel, wherein the semiconductor comprises InAs and the ferromagnetic insulator comprises EuS.

Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a plurality of source/drains disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, and a plurality of trenches, each trench extending to a corresponding one of the plurality of source/drains. A trench contact is formed in each of the trenches in contact with the corresponding source/drain. A recess is formed in a portion of each trench contact below a top surface of the cap. A bi-stable resistive system (BRS) material is deposited in each recess in contact with the portion of the trench contact. A source/drain contact is formed upon the BRS material, a portion of the trench contact, the BRS material, and a portion of the source/drain contact forming a reversible switch for each of the corresponding source/drains.