This application discloses a planar inductor. The planar inductor includes a first inductor module and a second inductor module that are connected in parallel. A direction of a magnetic line of the first inductor module is opposite to a direction of a magnetic line of the second inductor module, so that the magnetic lines can form a self-close loop in the planar inductor, and impact of a far magnetic field generated by the inductor on the outside, especially a nearby inductor, can be greatly reduced, thereby reducing crosstalk between the inductors, that is, reducing a phase noise, and increasing a Q value of the inductor. In addition, this application further provides a semiconductor chip that includes the planar inductor.

A semiconductor device having 3D inductor includes a first transverse inductor, a longitudinal inductor and a second transverse inductor. The first transverse inductor is formed on a first substrate, the second transverse inductor and the longitudinal inductor are formed on a second substrate. The second substrate is bonded to the first substrate to connect the first transverse inductor and the longitudinal inductor such that the first transverse inductor, the longitudinal inductor and the second transverse inductor compose a 3D inductor.

A semiconductor device has a substrate, a first circuit, a first inductor, a second circuit and a second inductor IND2. The substrate includes a first region and a second region, which are regions different from each other. The first circuit is formed on the first region. The first inductor is electrically connected with the first circuit. The second circuit is formed on the second regions. The second inductor is electrically connected with the second circuit and formed to face the first inductor. A penetrating portion is formed in the substrate. The penetrating portion is formed such that the penetrating portion surrounds one or both of the first circuit and the second circuit in plan view.

A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.

A method of forming a package structure includes: forming an inductor comprising a through-via over a carrier; placing a semiconductor device over the carrier; molding the semiconductor device and the through-via in a molding material; and forming a first redistribution layer on the molding material, wherein the inductor and the semiconductor device are electrically connected by the first redistribution layer.

A method is provided for fabricating thick silicon oxide structures, such as an embedded inductor. A Deep Reactive Ion Etch (DREI) etches the top silicon layer of a substrate to form high aspect ratio Si features, called trench texturing. The Si features are oxidized to form silicon oxide features. Adjacent Si features are separated by a trench width (S(0)), so that after oxidation, adjacent Si oxide features are formed separated by trench width (S(t)), where S(t)S(0) (e.g., S(t)=0). If the Si features have a width W.sub.Si(0)>1.2728 S(0), then the adjacent silicon oxide features form an amorphously merged silicon oxide feature with a planar top surface. The silicon oxide features have a height (H.sub.OX(t)) responsive to the trench width (S(0)), the Si feature width (W.sub.Si(t)), and the Si feature aspect ratio. After oxidation, inductor metal is deposited in trenches where W.sub.Si(0)<1.2728 S(0).

A microelectronic device may include a substrate, a component, a first plate, a second plate, and a shield. The component may be disposed at least partially within the substrate. The first plate may be disposed on a first side of the component. The second plate may be disposed on a second side of the component. The shield may be disposed around at least a portion of a periphery of the component.

A device includes a first metal layer including a first terminal outside the first coil and a second terminal within the inner area of the first coil. A second metal layer has a second coil. The second coil has a first terminal outside the second coil and a second terminal within its inner area. A first via electrically couples the second terminals of the first and second coils. A third metal layer has a third coil defining an inner area which at least partially overlaps the inner areas of the first and second coil. The third coil has a first terminal outside the third coil and a second terminal within its inner area. The second coil at least partially overlaps the third coil. A second via electrically couples together the first terminal of the second coil and the second terminal of the third coil.

Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

In a described example, an integrated circuit includes: a semiconductor substrate having a first surface and an opposite second surface; at least one dielectric layer overlying the first surface of the semiconductor substrate; at least one inductor coil in the at least one dielectric layer with a plurality of coil windings separated by coil spaces, the at least one inductor coil lying in a plane oriented in a first direction parallel to the first surface of the semiconductor substrate, the at least one inductor coil electrically isolated from the semiconductor substrate by a portion of the at least one dielectric layer; and trenches extending into the semiconductor substrate in a second direction at an angle with respect to the first direction, the trenches underlying the inductor coil and filled with dielectric replacement material.