A multilayer electronic device may include a plurality of dielectric layers stacked in a Z-direction that is perpendicular to an X-Y plane. The device may include a first conductive layer overlying one of the plurality of dielectric layers. The multilayer electronic device may include a second conductive layer overlying another of the plurality of dielectric layers and spaced apart from the first conductive layer in the Z-direction. The second conductive layer may overlap the first conductive layer in the X-Y plane at an overlapping area to form a capacitor. The first conductive layer may have a pair of parallel edges at a boundary of the overlapping area and an offset edge within the overlapping area that is parallel with the pair of parallel edges. An offset distance between the offset edge and at least one of the pair of parallel edges may be less than about 500 microns.

A multilayer capacitor includes a body including dielectric layers and internal electrodes, and external electrodes, wherein the body has first and second surfaces opposing each other in a first direction, third and fourth surfaces opposing each other in a second direction, and fifth and sixth surfaces opposing each other in a third direction perpendicular to the first and second directions. A length of a portion of the plurality of internal electrodes in the third direction in an intermediate region of the body in the first direction is greater than a length of the first surface or the second surface of the body in the third direction. The plurality of internal electrodes have a bottleneck structure between the intermediate region and at least one of the first and second surfaces, and wherein the bottleneck structure has a shape recessed into an inner portion of the body.

A multilayer capacitor includes a body including dielectric layers and internal electrodes, and external electrodes, wherein the body has first and second surfaces opposing each other in a first direction, third and fourth surfaces opposing each other in a second direction, and fifth and sixth surfaces opposing each other in a third direction perpendicular to the first and second directions. A length of a portion of the plurality of internal electrodes in the third direction in an intermediate region of the body in the first direction is greater than a length of the first surface or the second surface of the body in the third direction. The plurality of internal electrodes have a bottleneck structure between the intermediate region and at least one of the first and second surfaces, and wherein the bottleneck structure has a shape recessed into an inner portion of the body.

The present invention is directed to a multilayer capacitor and a circuit board containing the multilayer capacitor. The capacitor includes a main body containing a set of alternating dielectric layers and internal electrode layers wherein the set contains a first internal electrode layer and a second internal electrode layer and each internal electrode layer includes a top edge, a bottom edge opposite the top edge, and two side edges extending between the top edge and the bottom edge that define a main body of the internal electrode layer. Each internal electrode layer contains at least one lead tab extending from the top edge of the main body of the internal electrode layer and at least one lead tab extending from the bottom edge of the main body of the internal electrode layer, wherein at least one lead tab extending from the top edge of the main body of the internal electrode layer and at least one lead tab extending from the bottom edge of the main body of the internal electrode layer include a lateral edge aligned with a side edge of the main body of the internal electrode layer. External terminals are electrically connected to the internal electrode layers wherein the external terminals are formed on a top surface of the capacitor, a bottom surface of the capacitor opposing the top surface of the capacitor, and extending along an end surface between the top surface and the bottom surface.

The present invention is directed to a multilayer capacitor and a circuit board containing the multilayer capacitor. The capacitor includes a main body containing a set of alternating dielectric layers and internal electrode layers wherein the set contains a first internal electrode layer and a second internal electrode layer and each internal electrode layer includes a top edge, a bottom edge opposite the top edge, and two side edges extending between the top edge and the bottom edge that define a main body of the internal electrode layer. Each internal electrode layer contains at least one lead tab extending from the top edge of the main body of the internal electrode layer and at least one lead tab extending from the bottom edge of the main body of the internal electrode layer, wherein at least one lead tab extending from the top edge of the main body of the internal electrode layer and at least one lead tab extending from the bottom edge of the main body of the internal electrode layer include a lateral edge aligned with a side edge of the main body of the internal electrode layer. External terminals are electrically connected to the internal electrode layers wherein the external terminals are formed on a top surface of the capacitor, a bottom surface of the capacitor opposing the top surface of the capacitor, and extending along an end surface between the top surface and the bottom surface.

A disclosed high-density capacitor includes a top electrode having an electrically conducting material forming a three-dimensional structure. The three-dimensional structure includes a plurality of vertical portions extending in a vertical direction and horizontal portions, that are interleaved within the vertical portions and extend in a first horizontal direction. The high-density capacitor further includes a dielectric layer formed over the top electrode, and a bottom electrode including an electrically conducting material, such that the bottom electrode is separated from the top electrode by the dielectric layer. Further, the bottom electrode envelopes some of the plurality of vertical portions of the top electrode. The disclosed high-density capacitor further includes a plurality of support structures that are aligned with the first horizontal direction such that the horizontal portions of the top electrode are formed under respective support structures. The high-density capacitor has a capacitance that is proportional to the volume of the capacitor.

A disclosed high-density capacitor includes a top electrode having an electrically conducting material forming a three-dimensional structure. The three-dimensional structure includes a plurality of vertical portions extending in a vertical direction and horizontal portions, that are interleaved within the vertical portions and extend in a first horizontal direction. The high-density capacitor further includes a dielectric layer formed over the top electrode, and a bottom electrode including an electrically conducting material, such that the bottom electrode is separated from the top electrode by the dielectric layer. Further, the bottom electrode envelopes some of the plurality of vertical portions of the top electrode. The disclosed high-density capacitor further includes a plurality of support structures that are aligned with the first horizontal direction such that the horizontal portions of the top electrode are formed under respective support structures. The high-density capacitor has a capacitance that is proportional to the volume of the capacitor.

A method of manufacturing a winding capacitor package structure is provided. The method of manufacturing the winding capacitor package structure includes: forming a base layer on an inner bottom surface of a casing structure; placing a winding assembly and a part of a conductive assembly inside an accommodating space of the casing structure; sequentially forming a plurality of filling layers between the winding assembly and the casing structure; and then placing a bottom carrier frame on a bottom portion of the casing structure so as to match with the casing structure. The casing structure includes a main casing for enclosing the base layer and the filling layer and a retaining body inwardly bent from a bottom side of the main casing, and the base layer and the filling layer are retained and limited inside the casing structure by the retaining body.

A method of manufacturing a winding capacitor package structure is provided. The method of manufacturing the winding capacitor package structure includes: forming a base layer on an inner bottom surface of a casing structure; placing a winding assembly and a part of a conductive assembly inside an accommodating space of the casing structure; sequentially forming a plurality of filling layers between the winding assembly and the casing structure; and then placing a bottom carrier frame on a bottom portion of the casing structure so as to match with the casing structure. The casing structure includes a main casing for enclosing the base layer and the filling layer and a retaining body inwardly bent from a bottom side of the main casing, and the base layer and the filling layer are retained and limited inside the casing structure by the retaining body.

A ceramic electronic device includes: a ceramic main body of a parallelepiped shape having at least two edge faces facing each other, and having an internal electrode layer inside; and external electrodes formed on the two edge faces and having a structure in which a plated layer is formed on a ground layer having a metal, as a main component, and ceramic; the external electrodes have an extension region which extends to at least one of four side faces from the two edge faces, and a part of which corresponds to a corner portion of the ceramic main body and includes a portion with the ground layer and a first portion, without the ground layer, arranged at a position where one of the two end faces and one of the four side faces are connected; and the plated layer covers the ground layer and the first portion.