A multi-layer ceramic capacitor includes: a first region including a polycrystal including, as a main component, crystal grains free from intragranular pores; a second region that includes a polycrystal including, as a main component, crystal grains including intragranular pores and includes a higher content of silicon than a content of silicon in the first region; a capacitance forming unit including ceramic layers laminated along a first direction, and internal electrodes disposed between the ceramic layers; and a protective portion including a cover that covers the capacitance forming unit and constitutes a main surface facing in the first direction, a side margin constituting a side surface facing in a second direction orthogonal to the first direction, and a ridge constituting a connection portion, the connection portion connecting the main surface and the side surface to each other. The ceramic layers include the first region. The ridge includes the second region.

Disclosed is an assembly including a busbar that includes: a first layer that defines: first layer top and bottom surfaces; first layer first and second ends; and a first layer center region between the first layer first and second ends; and the first layer forms first layer perforations of different sizes about the first layer center region so perforations closer to the first layer first end are smaller than perforations spaced apart therefrom; a second layer that is disposed against and electrically isolated from the first layer bottom surface, wherein the second layer defines connector orifices having a same size as each other that are aligned with the first layer perforations; and a first capacitor supported against and electrically connected to the first layer top surface, wherein the first capacitor includes busbar connectors that respectively extend through the first layer perforations to electrically connect with the connector orifices.

Disclosed is an assembly including a busbar that includes: a first layer that defines: first layer top and bottom surfaces; first layer first and second ends; and a first layer center region between the first layer first and second ends; and the first layer forms first layer perforations of different sizes about the first layer center region so perforations closer to the first layer first end are smaller than perforations spaced apart therefrom; a second layer that is disposed against and electrically isolated from the first layer bottom surface, wherein the second layer defines connector orifices having a same size as each other that are aligned with the first layer perforations; and a first capacitor supported against and electrically connected to the first layer top surface, wherein the first capacitor includes busbar connectors that respectively extend through the first layer perforations to electrically connect with the connector orifices.

There is provided a multilayer electronic component in which a short circuit between the internal electrodes, a decrease in capacitance, a decrease in breakdown voltage, and the like, may be suppressed by controlling an area fraction occupied by a region in which an intensity of brightness in a capacitance formation portion is 110% or more and 126% or less of an average value of an intensity of brightness of a cover portion.

A capacitor that includes a substrate having a first principal surface and a second principal surface, a lower electrode on the first principal surface, a dielectric film on the lower electrode, and an upper electrode on the dielectric film, wherein at least one of the lower electrode and the upper electrode has, in plan view of the first principal surface, a first region having a rectangular shape, and at least one second region protruding from at least one side of the first region.

A method of manufacturing an electronic component that includes preparing unfired multilayer bodies each including main surfaces opposite to each other in a stacking direction, side surfaces opposite to each other in a width direction, and end surfaces opposite to each other in a length direction. One of the side surfaces of each of the unfired multilayer bodies is bonded to an adhesive sheet, and the other side surface of each of the unfired multilayer bodies is polished by rotating a polishing surface of a rotary polishing machine while contacting the other side surface. An insulating layer is formed on the polished other side surface. In the polishing of the other side surface, at least one of the rotary polishing machine and the adhesive sheet is moved relative to the other thereof to form a polish groove in the length direction.

The present disclosure provides a capacitor module including: a capacitor; a first housing having a hexahedron shape and having an inner space in which the capacitor is disposed, the first housing including a pair of cooling parts recessed inwards from a pair of parallel surfaces among outer side surfaces thereof such that a refrigerant flows, a pair of cooling channels disposed inside opposite side surfaces perpendicular to the surfaces of the pair of cooling parts such that the pair of cooling parts communicate with each other, and a through-hole configured to connect each of the cooling channels to the outside such that the refrigerant is introduced or discharged therethrough; and a cooling plate coupled to the first housing so as to seal the cooling parts.

A film capacitor device includes a capacitor body, a metal electrode on each of side surfaces of the capacitor body, an external electrode electrically connected to the metal electrode, and a bond bonding the metal electrode and the external electrode together. The capacitor body includes a plurality of unit stacks being stacked. The plurality of unit stacks each include a film stack including a plurality of dielectric films being stacked and a pair of protective films covering surfaces of the film stack. The plurality of unit stacks in the capacitor body are stacked with end faces of the plurality of unit stacks in a first direction (x-direction) being displaced.

A film capacitor device includes a capacitor body, a metal electrode on each of side surfaces of the capacitor body, an external electrode electrically connected to the metal electrode, and a bond bonding the metal electrode and the external electrode together. The capacitor body includes a plurality of unit stacks being stacked. The plurality of unit stacks each include a film stack including a plurality of dielectric films being stacked and a pair of protective films covering surfaces of the film stack. The plurality of unit stacks in the capacitor body are stacked with end faces of the plurality of unit stacks in a first direction (x-direction) being displaced.

A semiconductor device is provided that includes a substrate 10 with first and second opposing main surfaces, a circuit layer disposed on the first main surface, and a first resin body on a surface of the circuit layer opposite from the substrate. The circuit layer includes first and second electrode layers on a side of the semiconductor substrate, a dielectric layer disposed between the electrode layers, a first outer electrode electrically connected to the first electrode layer and extended to the surface of the circuit layer, and a second outer electrode electrically connected to the second electrode layer and extended to the surface of the circuit layer. The first resin body is between the first and second outer electrodes in a plan view, and in sectional view, a tip end of the first resin body is positioned higher than tip ends of the first and second outer electrodes.