A semiconductor device includes a semiconductor substrate having first and second main surfaces that oppose each other in a thickness direction, and a circuit layer disposed on the first main surface. The circuit layer includes a first electrode layer on a side of the semiconductor substrate, a second electrode layer that faces the first electrode layer, a dielectric layer disposed between the electrode layers, and a first outer electrode electrically connected to the first electrode layer through an opening in the dielectric layer. An end portion of the dielectric layer on a side of the first region is in contact with the first electrode layer, and in the dielectric layer, a size of the end portion in the thickness direction is smaller than a size of an inter-electrode portion between the first and second electrode layers in the thickness direction.

An electronic component includes a multilayer body including a multilayer main body including end surfaces at which internal nickel electrode layers are exposed, side gap portions, external nickel layers on the end surfaces of the multilayer body, and external copper electrode layers covering the end surfaces on which the external nickel layers are provided. A nickel-based oxide and/or a silicon-based oxide are provided between the external nickel layer and the external copper electrode layer. A nickel layer and a tin layer are provided outside the external copper electrode layer. In a cross section passing through a middle of the electronic component in the width direction and extending in the length direction and the lamination direction, a relationship of about 0.2≤Tea/Tem≤about 1.1 is satisfied.

The use of Atomic Layer Deposition (ALD) and Molecular Layer Deposition (MLD) applied to powders and intermediates of the MLCC fabrication process can provide significant advantages. Coating metal particles within a defined range of ALD cycles is shown to provide enhanced oxidation resistance. Surprisingly, a very thin ALD layer was found to substantially increase sintering temperature.

A capacitor unit formed by a capacitor integrated structure is provided. The capacitor integrated structure is cut to form capacitor units separated from each other, and each of the capacitor units includes: a substrate; an isolation layer located on the substrate; a capacitor stacked structure located on the isolation layer, wherein the isolation layer electrically isolates the substrate from the capacitor stacked structure; and two electrode connectors located on the capacitor stacked structure and being exposed.

A ceramic electronic component includes a multilayer chip in which dielectric layers, which contain ceramic as a main component, and internal electrode layers, which contain a first metal as a main component, are alternately stacked, wherein one face of first and second faces opposite to each other in a stack direction of each of the internal electrode layers is covered with a metal oxide film of a second metal that is more easily oxidized than the first metal and the other face of the first and second faces is not covered with the metal oxide film, or the one face is covered with the metal oxide film and an area of the metal oxide film covering the other face is smaller than an area of the metal oxide film covering the one face.

A dielectric ceramic composition comprising a main component comprising an oxide represented by:
U.sub.aX.sub.bY.sub.cZ.sub.d((Ca.sub.1-x-ySr.sub.xM.sub.y).sub.m(Zr.sub.1-u-vTi.sub.uHf.sub.v)O.sub.3).sub.1-a-b-c-d
wherein the elements defined by U, X, Y, Z and M and subscripts a, b, c, d, x, y, m, u and v are defined.

A multilayer capacitive element and a design method of the same are provided. The capacitive element includes a substrate having a groove, a first aspect ratio modulation structure, and a plurality of conductive layers and a plurality of dielectric layers. The first aspect ratio modulation structure is located in the groove to define the groove as a first region and a first modulation region, wherein an aspect ratio of the first modulation region is different from that of the first region. The plurality of conductive layers and the plurality of dielectric layers are alternately stacked in the groove.

A silicon capacitor may include a silicon substrate having a three-dimensional pattern, and a dielectric thin film disposed over the silicon substrate and having a structure with a crystal gradient form. A manufacturing method of a dielectric thin film capacitor may include etching a silicon substrate to form a three-dimensional pattern, depositing an amorphous thin film on the etched silicon substrate at a temperature below 300° C., and embedding crystalline grains in the deposited amorphous thin film by performing plasma treatment. A manufacturing method of a dielectric thin film capacitor may include etching a silicon substrate to form a three-dimensional pattern, depositing an amorphous thin film on the etched silicon substrate at a temperature below 300° C., and depositing a crystalline layer on the deposited amorphous thin film by performing plasma treatment.

A metal-oxide-metal (MOM) capacitor is provided in the present invention. The MOM capacitor includes a capacitor element, wherein the capacitor element includes a first electrode and a second electrode. A projection of the first electrode includes a closed pattern in the vertical projection direction. A projection of the second electrode is surrounded by the closed pattern of the projection of the first electrode in the vertical projection direction.

Provided is an improved multilayered ceramic capacitor and an electronic device comprising the multilayered ceramic capacitor. The multilayer ceramic capacitor comprises first conductive plates electrically connected to first external terminations and second conductive plates electrically connected to second external terminations. The first conductive plates and second conductive plates form a capacitive couple. A ceramic portion is between the first conductive plates and said second conductive plates wherein the ceramic portion comprises paraelectric ceramic dielectric. The multilayer ceramic capacitor has a rated DC voltage and a rated AC V.sub.PP wherein the rated AC V.sub.PP is higher than the rated DC voltage.