A method is provided for manufacturing a thin film transistor (TFT) backplate that includes a switch TFT and a drive TFT. The method is conducted such that each of the switch TFT and the drive TFT manufactured therewith includes a source electrode/a drain electrode and a gate electrode, and also includes an etching stopper layer, a semiconductor layer, and gate isolation layer that are disposed between the source electrode/the drain electrode and the gate electrode to form a TFT structure. The gate isolation layers of the switch TFT and drive TFT are formed of different materials, such as SiOx and Al.sub.2O.sub.3, or SiOx and SiNx, or Al.sub.2O.sub.3 and a mixture of SiNx and SiOx, such that electrical properties of the switch TFT and the drive TFT are made different.

The present application provides an array substrate and a manufacturing method thereof, and a display device, to solve the problem in the prior art that the resistance of the common electrode is large due to an improper layout of the common electrode so that the common electrode is easily affected by other signals to cause voltage fluctuation and thus the quality of the display is influenced. In the array substrate and the manufacturing method thereof, and the display device provided in the present application, since the first common electrode is provided in the source-drain metal layer and the second and third common electrodes are further formed, connection of the first, second and third common electrodes effectively enables a low-resistance common electrode, which is not easily influenced by other signals to cause voltage fluctuation, therefore, the quality of the display can be improved.

The present application provides an array substrate and a manufacturing method thereof, and a display device, to solve the problem in the prior art that the resistance of the common electrode is large due to an improper layout of the common electrode so that the common electrode is easily affected by other signals to cause voltage fluctuation and thus the quality of the display is influenced. In the array substrate and the manufacturing method thereof, and the display device provided in the present application, since the first common electrode is provided in the source-drain metal layer and the second and third common electrodes are further formed, connection of the first, second and third common electrodes effectively enables a low-resistance common electrode, which is not easily influenced by other signals to cause voltage fluctuation, therefore, the quality of the display can be improved.

A includes a switch TFT and a drive TFT. The switch TFT is formed of a first source and a first drain, a first gate, and a first etching stopper layer, and a first oxide semiconductor layer and first gate isolation layer sandwiched therebetween. The drive TFT is formed of a second source and a second drain, a second gate, and a second oxide semiconductor layer, and a first etching stopper layer and a second gate isolation layer sandwiched therebetween. The electrical properties of the switch TFT and the drive TFT are different. The switch TFT has a smaller subthreshold swing to achieve fast charge and discharge, and the drive TFT has a relatively larger subthreshold swing for controlling a current and a grey scale more precisely.

The present disclosure provides a thin film transistor (TFT) array substrate, its manufacturing method and a display device. The method includes steps of: forming patterns of a common electrode, a common electrode line, a gate line and a data line on a substrate by a single patterning process; forming an insulating layer; forming a pattern of an active layer by a single patterning process; forming a gate insulating layer and forming via-holes corresponding to the gate line, the data line and the active layer in the gate insulating layer by a single patterning process; and forming patterns of a pixel electrode, a gate electrode, a source electrode and a drain electrode by a single patterning process.

The present disclosure provides a thin film transistor (TFT) array substrate, its manufacturing method and a display device. The method includes steps of: forming patterns of a common electrode, a common electrode line, a gate line and a data line on a substrate by a single patterning process; forming an insulating layer; forming a pattern of an active layer by a single patterning process; forming a gate insulating layer and forming via-holes corresponding to the gate line, the data line and the active layer in the gate insulating layer by a single patterning process; and forming patterns of a pixel electrode, a gate electrode, a source electrode and a drain electrode by a single patterning process.

The present disclosure provides a display substrate assembly including a first substrate and a second substrate opposite to each other, the first substrate including a first region and a second region, and, a total thickness of functional layers within the first region being less than a total thickness of functional layers within the second region, of the first substrate. A thickness compensation layer is provided on at least one of the first substrate and the second substrate, a position of the thickness compensation layer corresponds to a position of the first region, and, a sum of thickness of a thickness of the thickness compensation layer and the total thickness of the functional layers within the first region equals to the total thickness of the functional layers within the second region.

Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

To provide a composition for a three-dimensional integrated circuit capable of forming a filling interlayer excellent in thermal conductivity also in a thickness direction, using agglomerated boron nitride particles excellent in the isotropy of thermal conductivity, disintegration resistance and kneading property with a resin. A composition for a three-dimensional integrated circuit, comprising agglomerated boron nitride particles which have a specific surface area of at least 10 m.sup.2/g, the surface of which is constituted by boron nitride primary particles having an average particle size of at least 0.05 μm and at most 1 μm, and which are spherical, and a resin (A) having a melt viscosity at 120° C. of at most 100 Pa.Math.s.