A method is for detecting a condition associated with a final phase of a plasma dicing process. The method includes providing a non-metallic substrate having a plurality of dicing lanes defined thereon, plasma etching through the substrate along the dicing lanes, wherein during the plasma etching infrared emission emanating from at least a portion of the dicing lanes is monitored so that an increase in infrared emission from the dicing lanes is observed as the final phase of the plasma dicing operation is entered, and detecting the condition associated with the final phase of the plasma dicing from the monitored infrared emission.

A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

A polishing assembly for polishing of silicon wafers includes a polishing pad, a polishing head assembly, a temperature sensor, and a controller. The polishing head assembly holds a silicon wafer to position the silicon wafer in contact with the polishing pad. The polishing head assembly selectively varies a removal profile of the silicon wafer. The temperature sensor collects thermal data from a portion of the polishing pad. The controller is communicatively coupled to the polishing head assembly and the temperature sensor. The controller receives the thermal data from the temperature sensor and operates the polishing head assembly to selectively vary the removal profile of the silicon wafer based at least in part on the thermal data.

A metrology target includes: a first structure arranged to be created by a first patterning process; and a second structure arranged to be created by a second patterning process, wherein the first structure and/or second structure is not used to create a functional aspect of a device pattern, and wherein the first and second structures together form one or more instances of a unit cell, the unit cell having geometric symmetry at a nominal physical configuration and wherein the unit cell has a feature that causes, at a different physical configuration than the nominal physical configuration due to a relative shift in pattern placement in the first patterning process, the second patterning process and/or another patterning process, an asymmetry in the unit cell.

At least three dark field images of a feature on a semiconductor wafer can be formed using an optical inspection system. Each of the at least three dark field images is from a different channel of the optical inspection system using an aperture that is fully open during image generation. The dark field images can be fused into a pseudo wafer image that is aligned with a corresponding design. This alignment can improve care area placement.

Disclosed are methods of advanced process control (APC) for particular processes. A particular process (e.g., a photolithography or etch process) is performed on a wafer to create a pattern of features. A parameter is measured on a target feature and the value of the parameter is used for APC. However, instead of performing APC based directly on the actual parameter value, APC is performed based on an adjusted parameter value. Specifically, an offset amount (which is previously determined based on an average of a distribution of parameter values across all of the features) is applied to the actual parameter value to acquire an adjusted parameter value, which better represents the majority of features in the pattern. Performing this APC method minimizes dimension variations from pattern to pattern each time the same pattern is generated on another region of the same wafer or on a different wafer using the particular process.

An apparatus includes a first and second stages. The first and second stages respectively hold a first and second substrates. The second stage being opposed to the first stage. A stress application portion applies a stress to the first substrate based on a first magnification value. A calculator calculates the first magnification value based on a flatness of the first substrate and a first equation. The first equation represents a relation between flatness of a third substrate, a second magnification value, and an amount of pattern misalignment between the third substrate and a fourth substrate bonded to the third substrate. A controller controls the stress application portion to apply a stress to the first substrate on the first stage based on the first magnification value while the first and second substrates are bonded to each other.

Provided are a deposition process monitoring system capable of detecting an internal state of a chamber in a deposition process, and a method of controlling the deposition process and a method of fabricating a semiconductor device using the system. The deposition process monitoring system includes a facility cover configured to define a space for a deposition process, a chamber located in the facility cover, covered with a translucent cover dome, and having a support on which a deposition target is placed, a plurality of lamps disposed in the facility cover, the lamps respectively disposed above and below the chamber, the lamps configured to supply radiant heat energy into the chamber during the deposition process, and a laser sensor disposed outside the chamber, the laser sensor configured to irradiate the cover dome with a laser beam and detect an intensity of the laser beam transmitted through the cover dome, wherein a state of by-products with which the cover dome is coated is determined based on the detected intensity of the laser beam.

A field-effect transistor comprises, on a substrate, a source electrode, a drain electrode, and a gate electrode; a semiconductor layer in contact with the source electrode and the drain electrode; wires individually electrically connected to the source electrode and the drain electrode; and a gate insulating layer that insulates the semiconductor layer from the gate electrode, wherein a connecting portion between the source electrode and the wire forms a continuous phase, and a connecting portion between the drain electrode and the wire forms a continuous phase, the portions constituting the continuous phases contain at least an electrically conductive component and an organic component, and integrated values of optical reflectance at a region of a wavelength of 600 nm or more and 900 nm or less on the wires are higher than integrated values of optical reflectance at a region of a wavelength of 600 nm or more and 900 nm or less on the source electrode and the drain electrode.

Monitoring operations of a polishing system includes obtaining a time-based sequence of reference images of a component of the polishing system performing operations during a test operation of the polishing system, receiving from a camera a time-based sequence of monitoring images of an equivalent component of an equivalent polishing system performing operations during polishing of a substrate, determining a difference value for the time-based sequence of monitoring images by comparing the time-based sequence of reference images to the time-based sequence of monitoring image using an image processing algorithm, determining whether the difference value exceeds a threshold, and in response to determining the difference value exceeds the threshold, indicating an excursion.