In a semiconductor device, a thinly-molded portion covering a whole of a heat dissipating surface portion of a lead frame and a die pad space filled portion are integrally molded from a second mold resin, because of which adhesion between the thinly-molded portion and lead frame improves owing to the die pad space filled portion adhering to a side surface of the lead frame. Also, as the thinly-molded portion is partially thicker owing to the die pad space filled portion, strength of the thinly-molded portion increases, and a deficiency or cracking is unlikely to occur.

A power module is provided. The power module includes a substrate, a power conversion chip that is disposed on the substrate and an insulating film that is formed on a structure in which the power conversion chip is disposed on the substrate. Additionally, the power module includes a metal mold that encases the structure that is coated with the insulating film. Additionally, the power module provides a simplified structure and improved heat dissipation performance compared to conventional power modules.

The present invention provides a silicone skeleton-containing polymer including a silicone skeleton shown by the following formula (1) and having a weight average molecular weight of 3,000 to 500,000.

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This can provide a silicone skeleton-containing polymer that can easily form a fine pattern with a large film thickness, and can form a cured material layer (cured film) that is excellent in various film properties such as crack resistance and adhesion properties to a substrate, electronic parts, and a semiconductor device, particularly a base material used for a circuit board, and has high reliability as a film to protect electric and electronic parts and a film for bonding substrates; and a photo-curable resin composition that contains the polymer, a photo-curable dry film thereof, a laminate using these materials, and a patterning process.

An interconnect structure includes a substrate, a dielectric layer on the substrate, a metal interconnect layer in the dielectric layer and in contact with the substrate, the metal interconnect layer having an upper surface flush with an upper surface of the dielectric layer, and a graphene layer on the metal interconnect layer. The graphene layer insulates a metal from air and prevents the metal from being oxidized by oxygen in the air, thereby increasing the queue time for the CMP process and the device reliability.

An interconnect structure includes a substrate, a dielectric layer on the substrate, a metal interconnect layer in the dielectric layer and in contact with the substrate, the metal interconnect layer having an upper surface flush with an upper surface of the dielectric layer, and a graphene layer on the metal interconnect layer. The graphene layer insulates a metal from air and prevents the metal from being oxidized by oxygen in the air, thereby increasing the queue time for the CMP process and the device reliability.

Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.

A resin having a small linear thermal expansion coefficient and a low absorbance is provided. The resin is characterized by including at least one structure selected from structures represented by the following general formulae (1) and (2):

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A display device and a manufacturing method thereof are provided. The display device includes: a first array substrate, a first opposite substrate, a second array substrate and a second opposite substrate stacked in sequence; the first array substrate comprises a first overlap portion overlapping with the first opposite substrate, a first extension portion extending from the first overlap portion, and the second array substrate comprises a second overlap portion overlapping with the second opposite substrate, a second extension portion extending from the second overlap portion; a side, facing the second extension portion, of the first extension portion comprises a first control IC, and a side, away from the first extension portion, of the second extension portion comprises a second control IC; and a space between the first and the second extension portions is filled with a heat dissipation component at least in an area where the first control IC is.

A fan-out packaging method includes: prepare circuit patterns on one side or both sides of a substrate; install electronic parts on one side or both sides of the substrate; prepare packaging layers on both sides of the substrate; the packaging layers on both sides of the substrate package the substrate, the circuit patterns, and the electronic parts, the packaging layers being made of a thermal-plastic material; wherein the substrate is provided with a via hole; both sides of the substrate are communicated by means of the via hole; a part of the packaging layers penetrate through the via hole when the packaging layers are prepared on both sides of the substrate; and the packaging layers on both sides of the substrate are connected by means of the via hole.

A fan-out packaging method includes: prepare circuit patterns on one side or both sides of a substrate; install electronic parts on one side or both sides of the substrate; prepare packaging layers on both sides of the substrate; the packaging layers on both sides of the substrate package the substrate, the circuit patterns, and the electronic parts, the packaging layers being made of a thermal-plastic material; wherein the substrate is provided with a via hole; both sides of the substrate are communicated by means of the via hole; a part of the packaging layers penetrate through the via hole when the packaging layers are prepared on both sides of the substrate; and the packaging layers on both sides of the substrate are connected by means of the via hole.