An object is to provide a technique capable of suppressing generation of a crack in a molding resin and suppressing entry of moisture from the outside. A semiconductor device includes a heat spreader, a semiconductor element provided on an upper surface of the heat spreader, an insulating sheet provided on a lower surface of the heat spreader, a lead frame joined to an upper surface of the semiconductor element via solder, and a molding resin that seals one end side of the lead frame, the semiconductor element, the heat spreader, and the insulating sheet. A hole is formed from an upper surface of the molding resin to a joining surface of the lead frame with the semiconductor element, and the hole is filled with a low Young's modulus resin having a Young's modulus lower than that of the molding resin.

A semiconductor device includes a semiconductor element, a first wiring member, a second wiring member, and a terminal. The semiconductor element includes a first main electrode and a second main electrode on a side opposite from the first main electrode. The first wiring member is connected to the first main electrode. The terminal has a first terminal surface connected to the second main electrode and a second terminal surface. The second terminal has four sides. Two of the four sides are parallel to a first direction intersecting the thickness direction, and other two sides of the four sides are parallel to a second direction perpendicular to the thickness direction and the first direction. The second wiring member is connected to the second terminal surface of the terminal through solder, and has a groove. The groove overlaps one or two of the four sides of the second terminal surface.

A component carrier including (a) a stack having at least one electrically conductive layer structure and at least one electrically insulating layer structure; (b) an optical component embedded within the stack, wherein the optical component comprises an optically active portion; (c) an opening formed within the stack, wherein the optical component and the opening are spatially arranged and configured such that an optical communication between the optically active portion and an exterior of the stack is enabled; and (d) a protection structure extending at least partially around the optically active portion and/or the opening. The protection structure protects the optically active portion from a resin flow during an embedding of the optical component in the stack. A method for manufacturing such a component carrier.

A method for making a semiconductor structure includes forming a first fin and a second fin over a substrate. The method includes forming one or more work function layers over the first and second fins. The method includes forming a nitride-based metal film over the one or more work function layers. The method includes covering the first fin with a patternable layer. The method includes removing a second portion of the nitride-based metal film from the second fin, while leaving a first portion of the nitride-based metal film over the first fin substantially intact.

Integrated circuit (IC) chips are provided. An IC chip according to the present corner area between an outer corner of the device region and an inner corner of the ring region. The ring region includes a first active region extending along a first direction, a first source/drain contact disposed partially over the first active region and extending along the first direction, and first gate structures disposed completely over the first active region and each extending lengthwise along the first direction. The corner area includes a second active region extending along a second direction that forms an acute angle with the first direction, a second source/drain contact disposed partially over the second active region and extending along the second direction, and second gate structures disposed over the second active region and each extending along the first direction.

A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.

An electronic package includes a patterned conductive layer and at least one conductive protrusion on the patterned conductive layer. The at least one conductive protrusion has a first top surface. The patterned conductive layer and the at least one conductive protrusion define a space. The electronic package further includes a first electronic component disposed in the space and a plurality of conductive pillars on the first electronic component. The conductive pillars have a second top surface. The first top surface is substantially level with the second top surface.

A method is provided for fabricating a semiconductor wafer having a device side, a back side opposite the device side and an outer periphery edge. Suitably, the method includes: forming a top conducting layer on the device side of the semiconductor wafer; forming a passivation layer over the top conducting layer, the passivation layer being formed so as not to extend to the outer periphery edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin coated over the passivation layer so as to have a smooth top surface at least in a region proximate to the outer periphery edge of the semiconductor wafer.

An electronic circuit device according to the present invention includes a base substrate including a wiring layer having a connection part, at least one electronic circuit element, and a re-distribution layer including a photosensitive resin layer, the photosensitive resin layer enclosing a surface on which a connection part of the electronic circuit element is formed and a side surface of the electronic circuit element and embedding a first wiring photo via, a second wiring photo via and a wiring, the first wiring photo via directly connected to the connection part of the electronic circuit element, the second wiring photo via arranged at the outer periphery of the electronic circuit element and directly connected to a connection part of the wiring layer, the wiring electrically connected to the first wiring photo via and the second wiring photo via on a same surface.

A semiconductor package includes a first semiconductor chip including a first surface and a second surface, and including a first active layer on a portion adjacent to the first surface; a first redistribution structure on the first surface of the first semiconductor chip, wherein the first redistribution structure includes a first area and a second area next to the first area; a second semiconductor chip mounted in the first area of the first redistribution structure, including a third surface, which faces the first surface, and a fourth surface, and including a second active layer on a portion adjacent to the third surface; a conductive post mounted in the second area of the first redistribution structure; a molding layer at least partially surrounding the second semiconductor chip and the conductive post on the first redistribution structure; and a second redistribution structure disposed on the molding layer and connected to the conductive post.