A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and a first encapsulant covering at least a portion of each of the inactive surface and a side surface of the semiconductor chip. A metal layer is disposed on the first encapsulant, and includes a first conductive layer and a second conductive layer, sequentially stacked. A connection structure is disposed on the active surface of the semiconductor chip, and includes a first redistribution layer electrically connected to the connection pad. A lower surface of the first conductive layer is in contact with the first encapsulant and has first surface roughness, and an upper surface of the first conductive layer is in contact with the second conductive layer and has second surface roughness smaller than the first surface roughness.

A semiconductor structure includes a molding, a device in the molding, and a RDL over the device and the molding. The RDL includes a first portion directly over a surface of the molding, and a second portion directly over a surface of the device. A bottom surface of the first portion is in contact with the surface of the molding, and a bottom surface of the second portion is in contact with the surface of the device. The bottom surface of the first portion of the RDL and the bottom surface of the second portion of the RDL are at different levels and misaligned from each other. A thickness of the first portion is greater than a thickness of the second portion.

Disclosed herein are cavity structures in integrated circuit (IC) package supports, as well as related methods and apparatuses. For example, in some embodiments, an IC package support may include: a cavity in a dielectric material, wherein the cavity has a bottom and sidewalls; conductive contacts at the bottom of the cavity, wherein the conductive contacts include a first material; a first peripheral material outside the cavity, wherein the first peripheral material is at the sidewalls of the cavity and proximate to the bottom of the cavity, and the first peripheral material includes the first material; and a second peripheral material outside the cavity, wherein the second peripheral material is at the sidewalls of the cavity and on the first peripheral material, and the second peripheral material is different than the first peripheral material.

In one example, a semiconductor device can comprise (a) an electronic device comprising a device top side, a device bottom side opposite the device top side, and a device sidewall between the device top side and the device bottom side, (b) a first conductor comprising, a first conductor side section on the device sidewall, a first conductor top section on the device top side and coupled to the first conductor side section, and a first conductor bottom section coupled to the first conductor side section, and (c) a protective material covering the first conductor and the electronic device. A lower surface of the first conductor top section can be higher than the device top side, and an upper surface of the first conductor bottom section can be lower than the device top side. Other examples and related methods are also disclosed herein.

A semiconductor device includes: a thick copper member in which a semiconductor chip is mounted; a printed circuit board that is disposed on a front surface of the thick copper member and provided with an opening exposing a part of the front surface of the thick copper member, a wiring pattern, and conductive vias connecting the pattern and the thick copper member; a semiconductor chip mounted on the front surface of the thick copper member exposed through the opening and connected to the pattern by a metal wire; an electronic component mounted on a front surface of the printed circuit board opposite to a side facing the thick copper member and connected to the pattern; and a cap or an epoxy resin sealing the front surface of the printed circuit board opposite to a side facing the thick copper member, the chip, the component, and the metal wire.

A SAW device includes a mounting substrate including a mounting surface, a SAW chip mounted on the mounting surface, a dummy chip mounted on the mounting surface, and a resin part covering the acoustic wave chip and the dummy chip. The dummy chip includes an insulating dummy substrate, and one or more dummy terminals which are located on a surface of the dummy substrate on the mounting surface side and are bonded to the mounting surface. The dummy chip configures an open end when electrically viewed from the mounting substrate side.

A method of forming an assembly is provided. The method includes attaching a packaged semiconductor device to a substrate. An isolation structure is formed and located between the packaged semiconductor device and the substrate. An underfill material is dispensed between the packaged semiconductor device and the substrate. The isolation structure prevents the underfill material from contacting a first conductive connection formed between the packaged semiconductor device and the substrate.

A package includes at least one memory component and an insulating encapsulation. The at least one memory component includes a stacked memory structure and a plurality of conductive posts. The stacked memory structure is laterally encapsulated in a molding compound. The conductive posts are disposed on an upper surface of the stacked memory structure. The upper surface of the stacked memory structure is exposed from the molding compound. The insulating encapsulation encapsulates the at least one memory component. The top surfaces of the conductive posts are exposed form the insulating encapsulation. A material of the molding compound is different a material of the insulating encapsulation.

A package substrate of a semiconductor package includes conductive lines of a first layer disposed on a first surface of a base layer and conductive lines of a second layer disposed on a second surface of the base layer. An opening hole located between a first remaining portion and a second remaining portion to separate the first and second remaining portions from each other. The first remaining portion is electrically connected to a first conductive line among the conductive lines of the second layer, and the second remaining portion is electrically connected to a second conductive line among the conductive lines of the second layer.

A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame. This differential in height reduces the span of wires used to form electrical connections within the semiconductor package. These reductions in the span of the wires reduces the chances of wire to wire and wire to die short circuiting because the wire sweep of the wires is reduced when the molding compound is placed.