An electronic package includes a patterned conductive layer and at least one conductive protrusion on the patterned conductive layer. The at least one conductive protrusion has a first top surface. The patterned conductive layer and the at least one conductive protrusion define a space. The electronic package further includes a first electronic component disposed in the space and a plurality of conductive pillars on the first electronic component. The conductive pillars have a second top surface. The first top surface is substantially level with the second top surface.

An integrated circuit includes a resistive material layer formed on a substrate, a metal layer formed on the resistive material layer, a bipolar transistor formed on the substrate, and a resistive element formed on the substrate. The bipolar transistor includes, as a sub-layer, the metal layer formed in a first region, and also includes a collector layer formed on the sub-collector layer. The resistive element is constituted by the resistive material layer formed in a second region.

An integrated circuit includes a resistive material layer formed on a substrate, a metal layer formed on the resistive material layer, a bipolar transistor formed on the substrate, and a resistive element formed on the substrate. The bipolar transistor includes, as a sub-layer, the metal layer formed in a first region, and also includes a collector layer formed on the sub-collector layer. The resistive element is constituted by the resistive material layer formed in a second region.

Provided are an electronic drive device and an electronic steering device, in each of which: a mounting substrate has one surface as a first surface on which a first heat generating component is mounted and the other surface as a second surface on which a second heat generating component is mounted; a first heat dissipation member is arranged in contact with the second surface at a position corresponding to a mounted position of the first heat generating component such that heat generated by the first heat generating component is dissipated to a motor housing; and a second heat dissipation member is arranged in contact with the first surface at a position corresponding to a mounted position of the second heat generating component such that heat generated by the second heat generating component is dissipated to a cover.

A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.

A semiconductor device includes a substrate, an active region provided in the substrate, a plurality of gate fingers provided on the active region, extending in an extension direction, and arranged in an arrangement direction orthogonal to the extension direction, and a gate connection wiring commonly connected to the plurality of gate fingers and provided between the plurality of gate fingers and a first side surface of the substrate, wherein when viewed from the arrangement direction, a first position where a first end of a first gate finger as a part of the plurality of gate fingers is connected to the gate connection wiring is closer to the first side surface than a second position where a first end of a second gate finger as another part of the plurality of gate fingers is connected to the gate connection wiring.

A semiconductor package includes; laterally stacked semiconductor blocks disposed side by side in a first horizontal direction on a redistribution structure, wherein each semiconductor block among the laterally stacked semiconductor blocks includes laterally stacked semiconductor chips, a heat dissipation plate, and a first molding member on the laterally stacked semiconductor chips.

A semiconductor package includes a package substrate, a lower semiconductor device arranged on the package substrate and including first through electrodes, first lower connection bumps arranged between the package substrate and the lower semiconductor device and electrically connecting the package substrate to the first through electrodes, a connecting substrate arranged on the package substrate and including second through electrodes, second lower connection bumps arranged between the package substrate and the connecting substrate and electrically connecting the package substrate to the second through electrodes, and an upper semiconductor device arranged on the lower semiconductor device and electrically connected to the first through electrodes and the second through electrodes.

Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.