This application discloses a chip package assembly, an electronic device, and a preparation method of a chip package assembly. The chip package assembly includes a package substrate, a chip, and a heat dissipation part. The package substrate includes an upper conductive layer, a lower conductive layer, and a conductive part connected between the upper conductive layer and the lower conductive layer. The chip includes a front electrode and a back electrode that are disposed opposite each other, the chip is embedded in the package substrate, the conductive part surrounds the chip, the front electrode is connected to the lower conductive layer, and the back electrode is connected to the upper conductive layer. The heat dissipation part is connected to a surface of the upper conductive layer that is away from the chip. The upper conductive layer, the lower conductive layer, and the conductive part each conduct heat.

A method includes attaching a power electronic substrate to a bottom of a frame. The frame has a box-like rectangular shape with an open top and an open bottom. The method further includes disposing an external conductive terminal on the frame. The external conductive terminal has at least one terminal stub that extends on to the front surface of the power electronic substrate. The method further includes welding the at least one terminal stub to at least one circuit trace disposed on the front surface of the power electronic substrate.

A semiconductor guide pin is disclosed. Specific implementations may include a heatsink, one or more substrates coupled together, one or more pressfit pins coupled to the one or more substrates, and two or more guide pins coupled to the one or more substrates, where the two or more guide pins may have a height greater than the one or more pressfit pins.

An electronic system is disclosed. In one example, the electronic system comprises an at least partially electrically conductive carrier, an electronic component, and an intermetallic connection structure connecting the carrier and the component. The intermetallic connection structure comprising an intermetallic mesh structure in a central portion of the intermetallic connection structure, and opposing exterior structures without intermetallic mesh and each arranged between the intermetallic mesh structure and the carrier or the component.

A semiconductor device includes an insulating layer having a first surface and a second surface opposite to the first surface. The semiconductor device includes at least one semiconductor element located on a side of the first surface. The semiconductor device includes a first metal sinter and a second metal sinter. The first metal sinter is in contact with the first surface of the insulating layer and the semiconductor element, and bonds the insulating layer and the semiconductor element. The second metal sinter is in contact with the second surface of the insulating layer.

An integrated circuit package includes first and second dies bonded to each other. The first die includes first die pads over a first device, first bonding pads over the first die pads, a first conductive via disposed between and electrically connected to a first one of the first die pads and a first one of the first bonding pads, and a first thermal via disposed between a second one of the first die pads and a second one of the first bonding pads and electrically insulated from the second one of the first die pads or the second one of the first bonding pads. The second die includes second bonding pads. The first one of the first bonding pads is connected to a first one of the second bonding pads. The second one of the first bonding pads is connected to a second one of the second bonding pads.

An integrated circuit package includes first and second dies bonded to each other. The first die includes first die pads over a first device, first bonding pads over the first die pads, a first conductive via disposed between and electrically connected to a first one of the first die pads and a first one of the first bonding pads, and a first thermal via disposed between a second one of the first die pads and a second one of the first bonding pads and electrically insulated from the second one of the first die pads or the second one of the first bonding pads. The second die includes second bonding pads. The first one of the first bonding pads is connected to a first one of the second bonding pads. The second one of the first bonding pads is connected to a second one of the second bonding pads.

A system and method of providing high bandwidth and low latency memory architecture solutions for next generation processors is disclosed. The package contains a substrate, a memory device embedded in the substrate via EMIB processes and a processor disposed on the substrate partially over the embedded memory device. The I/O pads of the processor and memory device are vertically aligned to minimize the distance therebetween and electrically connected through EMIB uvias. An additional memory device is disposed on the substrate partially over the embedded memory device or on the processor. I/O signals are routed using a redistribution layer on the embedded memory device or an organic VHD redistribution layer formed over the embedded memory device when the additional memory device is laterally adjacent to the processor and the I/O pads of the processor and additional memory device are vertically aligned when the additional memory device is on the processor.

According to an aspect of the disclosure, an example microelectronic device assembly includes a substrate, a microelectronic element electrically connected to the substrate, a stiffener element overlying the substrate, and a heat distribution device overlying the rear surface of the microelectronic element. The stiffener element may extend around the microelectronic element. The stiffener element may include a first material that has a first coefficient of thermal expansion (“CTE”). A surface of the stiffener element may face toward the heat distribution device. The heat distribution device may include a second material that has a second CTE. The first material may be different than the second material. The first CTE of the first material of the stiffener element may be greater than the second CTE of the second material of the heat distribution device.

A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip having a connection pad connected to the first redistribution layer; a vertical connection conductor electrically connected to the connection pad by the first redistribution layer; a core member having a first through-hole accommodating the semiconductor chip and a second through-hole accommodating the vertical connection conductor; an encapsulant filling the first and second through-holes; and a redistribution member including a second redistribution layer. The vertical connection conductor and the core member include a same material. A width of a lower surface of the vertical connection conductor is wider than that of an upper surface thereof, a width of a lower end of the first through-hole is narrower than that of an upper end thereof, and a width of a lower end of the second through-hole is narrower than that of an upper end thereof.