A heat dissipation structure assembly includes an elastic limiting member, a paste-type heat dissipation wall, a fitting member, a phase-change metal, and an assembling plate. The elastic limiting member is adapted to be disposed at a periphery of a heat source. The paste-type heat dissipation wall is adapted to be in contact with the periphery of the heat source. The fitting member is in contact with the paste-type heat dissipation wall and engaged with the elastic limiting member. The phase-change metal is adapted to be filled into a region among the fitting member, the paste-type heat dissipation wall, and the heat source. When a temperature of the phase-change metal exceeds a critical temperature, a state of the phase-change metal is changed to a liquid state. The assembling plate is connected to the fitting member, and the assembling plate is in contact with the paste-type heat dissipation wall.

Various embodiments may provide a semiconductor package. The semiconductor package may include a semiconductor chip, a first mold compound layer at least partially covering the semiconductor chip, and a redistribution layer over the first mold compound layer, the redistribution layer including one or more electrically conductive lines in electrical connection with the semiconductor chip. The semiconductor package may additionally include a second mold compound layer over the redistribution layer, and an antenna array over the second mold compound layer, the antenna array configured to be coupled to the one or more electrically conductive lines.

Various embodiments may provide a semiconductor package. The semiconductor package may include a semiconductor chip, a first mold compound layer at least partially covering the semiconductor chip, and a redistribution layer over the first mold compound layer, the redistribution layer including one or more electrically conductive lines in electrical connection with the semiconductor chip. The semiconductor package may additionally include a second mold compound layer over the redistribution layer, and an antenna array over the second mold compound layer, the antenna array configured to be coupled to the one or more electrically conductive lines.

A method of forming a semiconductor package is provided. The method includes forming a metallization stack over a semiconductor die. Polymer particles are mounted over the metallization stack. Each of the polymer particles is coated with a first bonding layer. A heat spreader lid is bonded with the semiconductor die by reflowing the first bonding layer. A composite thermal interface material (TIM) structure is formed between the heat spreader lid and the semiconductor die during the bonding. The composite TIM structure includes the first bonding layer and the polymer particles embedded in the first bonding layer.

A method of forming a semiconductor package is provided. The method includes forming a metallization stack over a semiconductor die. Polymer particles are mounted over the metallization stack. Each of the polymer particles is coated with a first bonding layer. A heat spreader lid is bonded with the semiconductor die by reflowing the first bonding layer. A composite thermal interface material (TIM) structure is formed between the heat spreader lid and the semiconductor die during the bonding. The composite TIM structure includes the first bonding layer and the polymer particles embedded in the first bonding layer.

A semiconductor package includes a semiconductor chip; a redistribution insulating layer including a first opening; an external connection bump including a first part in the first opening; a lower bump pad including a first surface in physical contact with the first part of the external connection bump and a second surface opposite to the first surface, wherein the first surface and the redistribution insulating layer partially overlap; and a redistribution pattern that electrically connects the lower bump pad to the semiconductor chip.

A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.

A semiconductor package includes a first semiconductor chip mounted on the package substrate, a second semiconductor mounted on the package substrate and set apart from the first semiconductor chip in a horizontal direction thereby forming a gap between the first semiconductor chip and the second semiconductor chip. The semiconductor package further includes a first thermal interface material layer formed in the gap and having a first modulus of elasticity and a second thermal interface material layer formed on each of the first semiconductor chip and the second semiconductor chip and having a second modulus of elasticity, wherein the first modulus of elasticity is less than the second modulus of elasticity.

This film-shaped firing material is a film-shaped firing material containing sinterable metal particles and a binder component, in which, when the average thickness of the portion of the film-shaped firing material excluding the edge portion is deemed 100%, the average thickness of the edge portion of the film-shaped firing material is at least 5% thicker than the average thickness of the portion of the film-shaped firing material excluding the edge portion.

A semiconductor package includes a redistribution structure, a plurality of semiconductor devices, and a plurality of heat dissipation films. The plurality of semiconductor devices mounted on the redistribution structure. The plurality of heat dissipation films are respectively disposed on and jointly covering upper surfaces of the plurality of semiconductor devices. A plurality of trenches are respectively extended between each two of the plurality of heat dissipations and extended between each two of the plurality of semiconductor devices.