A cyclic cooling embedded packaging substrate and a manufacturing method thereof are disclosed. The packaging substrate includes a dielectric material body, a chip, a first metal face, a second metal face and a first trace. The dielectric material body is provided with a packaging cavity, the chip is packaged in the packaging cavity, the first metal face is embedded in the dielectric material body, covers and is connected to a heat dissipation face of the chip. The second metal face is embedded in the dielectric material body, connected to a surface of the first metal face, and is provided with a first cooling channel pattern for forming a cooling channel. The first trace is arranged on a surface of the dielectric material body or embedded therein, and is connected with a corresponding terminal on an active face of the chip through a first conductive structure.

Methods, systems, apparatus, and articles of manufacture to control load distribution of integrated circuit packages are disclosed. An example apparatus includes a heatsink, a base of the heatsink to be thermally coupled to a semiconductor device, and a rigid plate to be coupled to the semiconductor device and the base of the heatsink, the rigid plate stiffer than the base, the rigid plate distinct from a bolster plate to which the heatsink is to be coupled.

In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very few physical (electrical) connections. The system includes multiple logical connections. The logical interconnections may be made with light transmission. A majority of physical connections may provide power. The physical interconnections may be sparse, periodic and regular. The exemplary system may include physical space (or gap) between the a pair of adjacent layers having few physical connections. The space may be generally set by the sizes of the connections. A constant flow of coolant (gaseous or liquid) may be maintained between the adjacent pair of layers in the space.

In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very few physical (electrical) connections. The system includes multiple logical connections. The logical interconnections may be made with light transmission. A majority of physical connections may provide power. The physical interconnections may be sparse, periodic and regular. The exemplary system may include physical space (or gap) between the a pair of adjacent layers having few physical connections. The space may be generally set by the sizes of the connections. A constant flow of coolant (gaseous or liquid) may be maintained between the adjacent pair of layers in the space.

A piezoelectric cooling system and method for driving the cooling system are described. The piezoelectric cooling system includes a first piezoelectric cooling element and a second piezoelectric cooling element. The first piezoelectric cooling element is configured to direct a fluid toward a surface of a heat-generating structure. The second piezoelectric cooling element is configured to direct the fluid to an outlet area after heat has been transferred to the fluid by the heat-generating structure.

A piezoelectric cooling system and method for driving the cooling system are described. The piezoelectric cooling system includes a first piezoelectric cooling element and a second piezoelectric cooling element. The first piezoelectric cooling element is configured to direct a fluid toward a surface of a heat-generating structure. The second piezoelectric cooling element is configured to direct the fluid to an outlet area after heat has been transferred to the fluid by the heat-generating structure.

Provided is a semiconductor package and a method of manufacturing the same, wherein in the semiconductor package, an area on a surface of a heat release metal layer pressed by a molding die is expanded and the molding die directly and uniformly compresses an upper substrate and/or a lower substrate, each of which does not include heat release posts so that contamination of a substrate occurring due to a molding resin may be prevented and molding may be stably performed.

Provided is a semiconductor package and a method of manufacturing the same, wherein in the semiconductor package, an area on a surface of a heat release metal layer pressed by a molding die is expanded and the molding die directly and uniformly compresses an upper substrate and/or a lower substrate, each of which does not include heat release posts so that contamination of a substrate occurring due to a molding resin may be prevented and molding may be stably performed.

A fluid control device includes a housing having plural surfaces defining a cavity within the housing. The housing includes an inlet to receive a fluid mixture and an outlet to direct the fluid mixture out of the housing. The fluid mixture includes a fluid combined with debris. A structure array is disposed within the cavity and includes plural structures. Each of the plural structures includes a first surface coupled with an internal surface of the housing and a second surface disposed a distance away from the internal surface of the housing. The structure array includes a first portion and a second portion. The first portion is configured to interfere with the fluid mixture to separate at least some of the debris from the fluid, and the second portion is configured to direct the fluid and at least some of the debris toward the outlet.

A cooling system and method for using the cooling system are described. The cooling system includes a plurality of individual piezoelectric cooling elements spatially arranged in an array extending in at least two dimensions, a communications interface and driving circuitry. The communications interface is associated with the individual piezoelectric cooling elements such that selected individual piezoelectric cooling elements within the array can be activated based at least in part on heat energy generated in the vicinity of the selected individual piezoelectric cooling elements. The driving circuitry is associated with the individual piezoelectric cooling elements and is configured to drive the selected individual piezoelectric cooling elements.