Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage step size in a sub-block that is more susceptible to wear extends the life of that sub-block, which extends the life of the block. For example, programming memory cells to fewer bits per cell in the region of the block (e.g., sub-block, word line) that is more susceptible to wear extends the useful life of that region, which extends the life of the block.

Technologies for conformal power delivery structures near high-speed signal traces are disclosed. In one embodiment, a dielectric layer may be used to keep a power delivery structure spaced apart from high-speed signal traces, preventing deterioration of signals on the high-speed signal traces due to capacitive coupling to the power delivery structure.

Embodiments described herein include electronic packages. In an embodiment, an electronic package comprises a die and a through substrate via that passes through the die. In an embodiment, the through substrate via is coupled to a backside pad on the die. In an embodiment, a first layer is over the backside pad, where the first layer comprises a first dielectric material. In an embodiment, a second layer is over the first layer, where the second layer comprises a second dielectric material. In an embodiment, a via is through the first layer and the second layer.

Various embodiments disclosed relate to methods of making omni-directional semiconductor interconnect bridges. The present disclosure includes semiconductor assemblies including a mold layer having mold material, a first filler material dispersed in the mold material, and a second filler material dispersed in the mold material, wherein the second filler material is heterogeneously dispersed.

A semiconductor package includes a lower substrate having a chip mounting region, an interconnection region surrounding the chip mounting region, and an outer region surrounding the interconnection region, and includes a lower wiring layer. A first solder resist pattern has first openings exposing bonding regions of the lower wiring layer. A semiconductor chip is on the chip mounting region and is electrically connected to the lower wiring layer. A second solder resist pattern is on the first solder resist pattern on the interconnection and outer regions and is spaced apart from the semiconductor chip, and includes second openings disposed on the first openings. An upper substrate covers the semiconductor chip, and includes an upper wiring layer. A vertical connection structure is on the interconnection region and electrically connects the upper and lower wiring layers. A solder resist spacer is on the second solder resist pattern on the outer region.

A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

An IC package structure and an IC package unit are disclosed. The IC package includes an array of metal wall grids formed into a panel, each one of the metal wall grids having a continuous and closed metal wall to surround an IC package unit with at least one IC chip/IC die disposed therein. Each IC chip/IC die has a top surface with a plurality of metal pads formed thereon. A panel-shaped metal layer is formed on entire back side of the panel of the array of metal wall grids and bonded to the metal wall of each metal wall grid. A panel-shaped rewiring substrate having a plurality of metal pillars is connected to each IC chip/IC die with each one of the plurality of metal pillars soldered with a corresponding one of the plurality of metal pads.

A package substrate based on a molding process may include an encapsulation layer, a support frame located in the encapsulation layer, a base, a device located on an upper surface of the base, a copper boss located on a lower surface of the base, a conductive copper pillar layer penetrating the encapsulation layer in the height direction, and a first circuit layer and a second circuit layer over and under the encapsulation layer. The second circuit layer includes a second conductive circuit and a heat dissipation circuit, the first circuit layer and the second conductive circuit are connected conductively through the conductive copper pillar layer, the heat dissipation circuit is connected to one side of the device through the copper boss and the base, and the first circuit layer is connected to the other side of the device.

Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Disclosed is a semiconductor device comprising a substrate including a cell array region and a connection region, an electrode structure extending in a first direction on the substrate and including vertically stacked electrodes having pad sections arranged stepwise on the connection region, a first contact plug connected to a first one of the pad sections, a pair of first vertical structures that penetrate the first one of the pad sections and are spaced apart from each other in a first direction by a first distance, a second contact plug connected to a second one of the pad section and having a vertical length that is greater than that of the first contact plug, and a pair of second vertical structures that penetrate the second one of the pad sections and are spaced apart from each other in the first direction by a second distance that is greater than the first distance.