Semiconductor dice are arranged on a substrate such as a leadframe. Each semiconductor die is provided with electrically-conductive protrusions (such as electroplated pillars or bumps) protruding from the semiconductor die opposite the substrate. Laser direct structuring material is molded onto the substrate to cover the semiconductor dice arranged thereon, with the molding operation leaving a distal end of the electrically-conductive protrusion to be optically detectable at the surface of the laser direct structuring material. Laser beam processing the laser direct structuring material is then performed with laser beam energy applied at positions of the surface of the laser direct structuring material which are located by using the electrically-conductive protrusions optically detectable at the surface of the laser direct structuring material as a spatial reference.

Methods and apparatus for chemical mechanical planarization (CMP) of a polymer or epoxy-based layer. In some embodiments, the method may comprise obtaining an endpoint for polymer or epoxy-based material for use in a CMP process, the CMP process configured to polish polymer or epoxy-based material, monitoring the polymer or epoxy-based layer with an endpoint detection apparatus configured to monitor polymer or epoxy-based material, polishing the polymer or epoxy-based layer with the CMP process, detecting when the polymer or epoxy-based layer has reached the endpoint for the CMP process, and halting the CMP process when the endpoint is detected. The endpoint detection apparatus may further comprise an optical detection apparatus configured to operate at a wavelength of approximately 200 nm to approximately 1700 nm to reduce step height of the polymer or epoxy-based layer.

Multichip technology, where several discrete chips are assembled or are fabricated on a single substrate can offer many advantages, including better scaling and better yield. However, existing methods of connecting the individual chips on a substrate, leaves these devices operating at much slower rates than their individual chips are capable of operating. Disclosed are systems and methods for fast interconnect structures between chips in a multi die setup, where density, bandwidth, power consumption and other interconnect operating parameters are improved.

The invention relates to a method (110) for producing an electrically conductive connection (112, 112) on a substrate (114), comprising the following steps: a) providing a substrate (114), wherein the substrate (114) is configured for receiving an electrically conductive connection (112, 112); b) providing a reservoir of an electrically conductive liquid alloy, wherein the reservoir has a surface at which the alloy has an insulating layer; c) providing a capillary (120) configured for taking up the electrically conductive liquid alloy; d) penetrating of a tip (122) of the capillary (120) under the surface of the reservoir and taking up of a portion of the alloy from the reservoir; and e) applying the portion of the alloy at least partly to the substrate (114) in such a manner that an electrically conductive connection (112, 112) is formed from the alloy on the substrate (114), wherein the alloy remains on the substrate (114) by adhesion. The invention furthermore relates to a method for producing a microelectronic device (124) and to a microelectronic device (124), in particular a transistor (130).

A method for producing electronic devices includes fixing a die that includes an electronic component with integral contacts to a dielectric substrate. After fixing the die, a conductive trace is printed over both the dielectric substrate and at least one of the integral contacts, so as to create an ohmic connection between the conductive trace on the substrate and the electronic component.

An apparatus for securing a wafer includes a chuck, at least one O-ring disposed on the chuck, a vacuum system connected to the chuck, such that the vacuum system comprises a plurality of vacuum holes through the chuck connected to one or more vacuum pumps, and a controller configured to control the height of the at least one O-ring relative to the top surface of the chuck. The controller is connected to pressure sensors capable of detecting a vacuum. The at least one O-ring may include a plurality of O-rings.

Development of smart objects with electronic functions requires integration of printed components with IC chips or dies. Conventional chip or die bonding including wire bonding, flip chip bonding, and soldering may not be applicable to chip or die attachment on low temperature plastic surfaces used in physical objects. Printing conductive connection traces requires a smooth interface between contact pads of a chip and the surface of the physical object. In order to address this issue of chip/die attachment to a physical object, this disclosure provides embodiments to construct a fixture on a chip or die for attachment and electrical connection onto a physical object by printing operations and/or ACF bonding methods.

Place a first semiconductor chip onto an alignment carrier with protrusions of the semiconductor chip inserted into corresponding cavities of the alignment carrier, so that the protrusions and cavities locate the semiconductor chip with interconnect contacts overlying a window that is formed through the alignment carrier. Place a second semiconductor chip onto the alignment carrier with protrusions of the second semiconductor chip inserted into cavities of the alignment carrier, so that the protrusions and cavities locate the second semiconductor chip with interconnect contacts of the second semiconductor chip adjacent to the interconnect contacts of the first semiconductor chip and overlying the window. Fasten the semiconductor chips to the alignment carrier. Touch contacts of a interconnect bridge against the interconnect contacts of the first and second semiconductor chips by putting the interconnect bridge through the window.

Panel level packaging (PLP) with high accuracy and high scalability is disclosed. The PLP employs an alignment carrier with a low coefficient of expansion which is configured with die regions having local die alignment marks. For example, local die alignment marks are provided for each die attach region. Depending on the size of the panel, it may be segmented into blocks, each with die regions with local die alignment marks. In addition, a block includes an alignment die region configured for attaching an alignment die. Linear and non-linear positional errors are reduced due to local die alignment marks and alignment dies. The use of local die alignment marks and alignment dies results in increase yields as well as scaling, thereby improving throughput and decreasing overall costs.

A system, method, and silicon chip package for providing connections between a die of a silicon chip package and external leads of the silicon chip package is disclosed. The connections are formed using a pre-mold etched with a trace pattern. The trace pattern provides rigid traces that connect the die with the external leads.