An object of the present invention is to suppress a crack in a sealing resin and a warpage in a semiconductor device in a power semiconductor device. A power semiconductor device includes: a semiconductor element; a terminal; a chassis; and a sealing resin sealing the semiconductor element and the terminal in the chassis. The sealing resin includes: a first sealing resin covering at least the semiconductor element; and a second sealing resin formed on an upper portion of the first sealing resin, and in an operation temperature of the semiconductor element, the first sealing resin has a smaller linear expansion coefficient than the second sealing resin, and a difference of a linear expansion coefficient between the first sealing resin and the terminal is smaller than a difference of a linear expansion coefficient between the second sealing resin and the terminal.

A semiconductor device includes a semiconductor part, first and second electrodes, and first and second protective films. The first electrode is provided on the semiconductor part. The first protective film is provided on the semiconductor part and covers an outer edge of the first electrode. The second electrode is provided on the first electrode. The second electrode includes an outer edge partially covering the first protective film. The second protective film is provided on the semiconductor part and covers the first protective film and the outer edge of the second electrode.

Provided is a semiconductor package modularized and manufactured by preparing a main block for putting on a semiconductor chip, an insulator, and one or more sub block, preparing the semiconductor chip, preparing an adhesive used in attaching the semiconductor chip, attaching the semiconductor chip to an upper surface or upper and lower surfaces of the main block, performing an electrical connection of the semiconductor chip, preparing a substrate comprising a pattern enabling an electrical connection and vertically attaching one side of the main block to the pattern of the substrate to enable an electrical connection. In the semiconductor package above, an accumulation rate increases on the substrate due to a vertically arranged structure of the semiconductor chips and a heat emission area is enlarged to improve a heat emission effect.

In one example, a semiconductor device includes a substrate that comprises a substrate conductor material. An electronic component has a first component terminal that comprises a first component terminal conductor material and a second component terminal that comprises a second component terminal conductor material. An interconnect comprises an interconnect conductor material, a component end, and a substrate end. The second component terminal is attached to the substrate with a first intermetallic bond, the component end of the interconnect is attached to the first component terminal with a second intermetallic bond, and the substrate end of the interconnect is attached to the substrate with a third intermetallic bond. Other examples and related methods are also disclosed herein.

A manufacturing method of an electronic-component-mounted module includes a step of forming a laminate of: a ceramic substrate board, a circuit layer made of aluminum or aluminum alloy on the ceramic substrate board, a first silver paste layer between the circuit layer and one surface of an electronic component, the electronic component, a lead frame made of copper or copper alloy, and a second silver paste layer between the other surface of the electronic component and the lead frame; and a step of batch-bonding bonding the circuit layer, the electronic component, and the lead frame at one time by heating the laminate to a heating temperature of not less than 180° C. to 350° C. inclusive with adding a pressure of 1 MPa to 20 MPa inclusive in a laminating direction on the laminate, to sinter the first and second silver paste layers and form first and second silver-sintered bonding layers.

In a wiring member, an element connection portion, a plate connection portion, and an upper surface portion are at height positions different from one another. The element connection portion has a through hole, and the plate connection portion has a through hole and a chamfer. The upper surface portion which is not connected to another portion, has projections asymmetrically disposed on both side surfaces thereof. Owing to these features, the type, the orientation, and the front and the back of the wiring member can be easily distinguished. Accordingly, it is possible to prevent incorrect assembling of the wiring member in a semiconductor module.

The present invention provides a packaging method and a packaging structure for a cascode power electronic device, in which a hetero-multiple chip scale package is used to replace the traditional die bonding and wire bonding packaging method. The cascode power electronic device can reduce the inductance resistance and thermal resistance of the connecting wires and reduce the size of the package; and increase the switching frequency of power density. The chip scale package of the present invention uses more than one gallium nitride semiconductor die, more than one diode, and more than one metal oxide semiconductor transistor. The package structure can use TO-220, quad flat package or other shapes and sizes; the encapsulation process of the traditional epoxy molding compounds can be used in low-power applications; and the encapsulation process of ceramic material can be used in high-power applications.

A method of manufacturing a cascode HEMT semiconductor device including a lead frame, a die pad with an indentation attached to the lead frame, and a HEMT die attached to the die pad. The HEMT die includes a HEMT source and a HEMT drain on a first side, and a HEMT gate on a second side. The device further includes a MOSFET die attached to the source of the HEMT die, and the MOSFET die includes a MOSFET source, a MOSFET gate and a MOSFET drain. The MOSFET drain is connected to the HEMT source, and the MOSFET source includes a MOSFET source clip. The MOSFET source clip includes a pillar so to connect the MOSFET source to the HEMT gate, and the connection between the MOSFET source to the HEMT gate is established by a conductive material.

A method of forming a semiconductor device includes providing a carrier comprising a die attach pad, providing a semiconductor die that includes a bond pad disposed on a main surface of the semiconductor die, and providing a metal interconnect element, arranging the semiconductor die on the die attach pad such that the bond pad faces away from the die attach pad, and welding the metal interconnect element to the bond pad, wherein the bond pad comprises first and second metal layers, wherein the second metal layer is disposed between the first metal layer and a semiconductor body of the semiconductor die, wherein a thickness of the first metal layer is greater than a thickness of the second metal layer, and wherein the first metal layer has a different metal composition as the second metal layer.

A semiconductor chip package is provided with improved connections between different components within the package. The semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate.