A method of manufacturing a semiconductor device includes forming a cell chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer, flipping the cell chip, exposing a rear surface of the source layer by removing the first substrate from the cell chip, performing surface treatment on the rear surface of the source layer to reduce a resistance of the source layer, forming a peripheral circuit chip including a second substrate and a circuit on the second substrate, and bonding the cell chip including the source layer with a reduced resistance to the peripheral circuit chip.

A method of fabricating an integrated circuit (IC) includes forming a dielectric layer on a substrate having a plurality of the IC. A thin-film resistor (TFR) layer is deposited on the dielectric layer, and an underlayer (UL) including carbon is formed on the TFR layer. A hard mask layer including silicon is formed on the UL. Masked etching of the hard mask layer transfers a pattern of a photoresist layer onto the hard mask layer to form a hard mask layer pattern. Masked etching of the UL transfers the hard mask layer pattern onto the UL to form a UL pattern. Masked etching of the TFR layer transfers the UL pattern onto the TFR layer to form a TFR layer pattern including a matched pair of TFRs. The matched pair of TFRs are generally included in circuitry configured together for implementing at least one function.

An electronic device includes a substrate, a first silicon nitride film provided on the substrate, a silicon oxide film provided on the first silicon nitride film, a capacitor provided on the silicon oxide film, and an interconnect electrically connected to the capacitor. The interconnect is disposed apart from the first silicon nitride film. In a plan view, an outer perimeter of the silicon oxide film is inside an outer perimeter of the first silicon nitride film.

A wafer arrangement comprises a carrier wafer (CW) having a top surface divided into a regular pattern (RP) of first CA (SA1, ARS) and second surface areas (SA2, PES), wherein each first surface area is assigned to an adjacently applied respective separate second surface area to form together a combined filter area. Spots of thin film piezoelectric material are bonded to the first surface areas. Circuits of LC elements (PES) are formed integrally on the second surface areas from a multi-level metallization (ML1, ML2). The LC elements of each metallization level being embedded in a dielectric.

A surface-mounted LC device that includes a substrate having a first surface, multiple inductors formed on the first surface and formed respectively by multiple coiled conductor patterns, a first insulating layer covering the multiple coiled conductor patterns, and a capacitor that is formed on the first insulating layer by a planar electrode. Moreover, the planar electrode covers first zones in which portions of the coiled conductor patterns are adjacent to each other and current directions are opposite to each other in a plan view of the surface-mounted LC device.

A capacitance element that includes a first lower electrode and a second lower electrode arranged adjacent to each other in a Y-axis direction on a substrate. A first dielectric layer is on the first lower electrode, and a second dielectric layer is on the second lower electrode. A first upper electrode and a second upper electrode are arranged adjacent to each other in an X-axis direction on the first dielectric layer, and a third upper electrode and a fourth upper electrode are arranged adjacent to each other in an X-axis direction on the second dielectric layer. Interlayer conductors are respectively in contact with the first through fourth upper electrodes. A first connection conductor connects the second interlayer conductor and the fourth interlayer conductor to each other.

A discrete field coupled capacitor with a cross-connected capacitor-pair, such as for use as a discrete bypass capacitor. The FCC includes a first port with first and second terminals, and a second port with third and fourth terminals. A first capacitor structure is connected between the first and second terminals, and a second capacitor structure connected between the third and fourth terminals. A cross-connect structure includes a first cross-connection to connect the first terminal to the third terminal, and a second cross-connection to connect the second terminal to the fourth terminal, to cross-connect the first and second capacitor structures. The capacitor structures have respective parasitic ESL, and can be disposed in proximity to effect a pre-defined ESL field coupling with reverse phasing to reduce parasitic ESL. The FCC can be constructed as a PCB or monolithic device. In a PCB four-layer construction, the cross-connections can be formed on respective mid-layers.

A capacitive element using VNW FETs is provided. First and second components each constituting a transistor are arranged in an X direction. From the first component, a first gate interconnect extends away from the second component, and a first top interconnect and a first bottom interconnect extend toward the second component. From the second component, a second gate interconnect extends toward the first component, and a second top interconnect and a second bottom interconnect extend away from the first component. The first top interconnect, the first bottom interconnect, and the second gate interconnect are connected.

A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.

A substrate and a method of manufacturing the same, and an electronic apparatus are provided. The substrate includes: a base substrate, a peripheral circuit, and a common electrode lead. The base substrate includes a working area, a non-working area located outside the working area, and an outer contour edge, the non-working area including a peripheral circuit area adjacent to the working area and a non-circuit area away from the working area; the peripheral circuit being arranged in the peripheral circuit area; the common electrode lead being arranged along at least a portion of the outer contour edge of the base substrate; the common electrode lead being arranged in the non-working area and extending along at least the portion of the outer contour edge; the peripheral circuit area being provided with the peripheral circuit, and the peripheral circuit being absent in the non-circuit area.