Methods/structures of forming thin film resistors using interconnect liner materials are described. Those methods/structures may include forming a first liner in a first trench, wherein the first trench is disposed in a dielectric layer that is disposed on a substrate. Forming a second liner in a second trench, wherein the second trench is adjacent the first trench, forming an interconnect material on the first liner in the first trench, adjusting a resistance value of the second liner, forming a first contact structure on a top surface of the interconnect material, and forming a second contact structure on the second liner.

An example of an apparatus includes a plurality of memory cells. At least a portion of the memory cells have a bottom electrode with each bottom electrode being at least partially electrically isolated from remaining ones of the bottom electrodes. At least one resistive interconnect electrically couples two or more of the bottom electrodes. The resistive interconnect is arranged to discharge at least a portion of excess charge from the two or more bottom electrodes. Additional apparatuses and methods of forming the apparatuses are disclosed.

The embodiments of the present disclosure provide a flexible touch substrate and a method for fabricating the same, and a touch display device and relate to touch control technology. Deformation or crack of the touch electrode pattern when the flexible touch substrate is bent, and can realize large curvature bending. The flexible touch substrate includes a flexible base substrate, touch electrode patterns disposed on a first surface of the flexible base substrate, and at least one groove on at least one of the first surface and a second surface opposite the first surface of the flexible base substrate, wherein a projection of the groove on the base substrate is within a projection of a gap between the touch electrode patterns on the base substrate.

An apparatus having a power converter circuit having a first active layer having a first set of active devices disposed on a face thereof, a first passive layer having first set of passive devices disposed on a face thereof, and interconnection to enable the active devices disposed on the face of the first active layer to be interconnected with the non-active devices disposed on the face of the first passive layer, wherein the face on which the first set of active devices on the first active layer is disposed faces the face on which the first set of passive devices on the first passive layer is disposed.

A semiconductor device includes a first electrode; a second electrode which is apart from the first electrode; and a dielectric layer between the first electrode and the second electrode. The dielectric layer may include a base material including an oxide of a base metal, the base material having a dielectric constant of about 20 to about 70, and co-dopants including a Group 3 element and a Group 5 element. The Group 3 element may include Sc, Y, B, Al, Ga, In, and/or Tl, and the Group 5 element may include V, Nb, Ta, N, P, As, Sb, and/or Bi.

A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.

A semiconductor device includes: a metal thin film disposed on a semiconductor substrate; and first and second contact structures disposed on the metal thin film, wherein the first and second contact structures are laterally spaced from each other by a dummy layer that comprises at least one polishing resistance material.

A passive component includes a substrate having insulating properties and having a surface having a recess, a bottom electrode filling at least a portion of the recess, a dielectric film provided on a surface of the bottom electrode, and a top electrode opposite to the bottom electrode with the dielectric film interposed therebetween. In a height direction perpendicular to the surface of the substrate, a dimension of the bottom electrode is larger than a dimension of the dielectric film.

An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer.

Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.