Solid-state transducers (“SSTs”) and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. The SST can further include a plurality of first contacts at the first side and electrically coupled to the first semiconductor material, and a plurality of second contacts extending from the first side to the second semiconductor material and electrically coupled to the second semiconductor material. An interconnect can be formed between at least one first contact and one second contact. The interconnects can be covered with a plurality of package materials.

Disclosed is a semiconductor module including a substrate, a first semiconductor layer positioned on the substrate, an insulator positioned in a partial region on the first semiconductor layer, a second semiconductor layer positioned on the insulator, a first semiconductor device formed on the first semiconductor layer, and a second semiconductor device formed on the second semiconductor layer, wherein one of the first semiconductor layer and the second semiconductor layer includes gallium oxide (Ga.sub.2O.sub.3) and the other includes silicon (Si).

A semiconductor device 100 has a power transistor N1 of vertical structure and a temperature detection element 10a configured to detect abnormal heat generation by the power transistor N1. The power transistor N1 includes a first electrode 208 formed on a first main surface side (front surface side) of a semiconductor substrate 200, a second electrode 209 formed on a second main surface side (rear surface side) of the semiconductor substrate 200, and pads 210a-210f positioned unevenly on the first electrode 208. The temperature detection element 10a is formed at a location of the highest heat generation by the power transistor N1, the location (near the pad 210b where it is easiest for current to be concentrated) being specified using the uneven positioning of the pads 210a-210f.

A semiconductor device 100 has a power transistor N1 of vertical structure and a temperature detection element 10a configured to detect abnormal heat generation by the power transistor N1. The power transistor N1 includes a first electrode 208 formed on a first main surface side (front surface side) of a semiconductor substrate 200, a second electrode 209 formed on a second main surface side (rear surface side) of the semiconductor substrate 200, and pads 210a-210f positioned unevenly on the first electrode 208. The temperature detection element 10a is formed at a location of the highest heat generation by the power transistor N1, the location (near the pad 210b where it is easiest for current to be concentrated) being specified using the uneven positioning of the pads 210a-210f.

A semiconductor integrated circuit device includes a core region and an IO region on a chip. In an IO cell row placed in the IO region, a first power supply line extending in the X direction in a low power supply voltage region has a portion protruding to the core region. A signal IO cell has a reinforcing line that connects a second power supply line extending in the X direction in the low power supply voltage region and a third power supply line extending in the X direction in a high power supply voltage region, the reinforcing line extending in the Y direction in a layer above the second and third power supply lines.

A mount board has a plurality of terminals electrically connected to a plurality of pins of a semiconductor device, and a conductor pattern. An electrostatic withstand voltage test device includes a metal plate on which the mount board is installed, a power supply for applying a voltage to the metal plate, an insulator disposed between the metal plate and the mount board, a switch circuit connected between the terminals and ground wiring, and a controller for controlling the switch circuit. The switch circuit includes a plurality of first switches provided corresponding to the terminals and each connecting a corresponding terminal to the ground wiring. The controller turns on at least one first switch selected from the first switches when an electric charge stored in the conductor pattern is discharged to the ground wiring through the semiconductor device.

In an IO region of a semiconductor integrated circuit device, placed is an IO cell row including a signal IO cell and a power IO cell supplying a first power supply. The power IO cell includes first and second external terminals connected to an external connection pad and an electrostatic discharge (ESD) protection device formed at least in a region between the first and second external terminals. The first external terminal is placed at a position having an overlap in the Y direction with a power supply line for a second power supply.

An output circuit includes: a first input transistor that is provided between a first power supply line and a first intermediate node; a second input transistor that is provided between a second intermediate node and a second power supply line; a first cascode transistor that is provided between the first intermediate node and an output node, and receives a first clip voltage from a first voltage generation circuit; a second cascode transistor that is provided between the output node and the second intermediate node, and receives a second clip voltage from a second voltage generation circuit; a first switch transistor that is provided between the first intermediate node and a gate of the first cascode transistor, and turns on during power down; and a second switch transistor that is provided between the second intermediate node and a gate of the second cascode transistor, and turns on during power down.

A semiconductor device including a protected element, a contact region, wiring, and a channel stopper region. The protected element is configured including a p-n junction diode between an anode region and a cathode region, and is arranged in an active layer of a substrate. The periphery of the diode is surrounded by an element isolation region. The contact region is arranged at a portion on a main face of the anode region, and is set with a same conductivity type as the anode region, and set with a higher impurity concentration than the anode region. The wiring is arranged over the diode. One end portion of the wiring is connected to the contact region and another end portion extends over a passivation film. The channel stopper region is arranged at a portion on the main face of the anode region under the wiring between the contact region and the element isolation region, and is set with an opposite conductivity type to the contact region.

Provided is a display substrate, which includes a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of signal input pads, a data fan-out line layer, and a plurality of resistance compensation units. The substrate includes a display region and a bezel region located region on a periphery of the display region, and the bezel region includes a signal access region located on a side of the display region and a fan-out region located between the display region and the signal access region. The data fan-out line layer and the plurality of resistance compensation units are disposed in the fan-out region, and the data fan-out line layer includes a plurality of data fan-out lines. At least one resistance compensation unit includes a semiconductor structure. At least one data fan-out line is connected in series with and electrically connected to at least one resistance compensation unit.