A capacitor that includes a substrate having a first principal surface and a second principal surface, a lower electrode on the first principal surface, a dielectric film on the lower electrode, and an upper electrode on the dielectric film, wherein at least one of the lower electrode and the upper electrode has, in plan view of the first principal surface, a first region having a rectangular shape, and at least one second region protruding from at least one side of the first region.

A capacitor that includes a substrate having a first principal surface and a second principal surface, a lower electrode on the first principal surface, a dielectric film on the lower electrode, and an upper electrode on the dielectric film, wherein at least one of the lower electrode and the upper electrode has, in plan view of the first principal surface, a first region having a rectangular shape, and at least one second region protruding from at least one side of the first region.

A capacitor that can make a failure mode into an open mode even when a short circuit caused by insulation breakdown occurs in a dielectric layer is provided. The capacitor includes: a substrate; an MIM structure disposed on the Substrate, the MIM structure including a dielectric layer, a bottom electrode layer disposed on one side of the dielectric layer and composed of a first conductive material, and a top electrode layer disposed on the other side of the dielectric layer; a first external electrode disposed on the substrate; a second external electrode disposed on the substrate; and a connection conductor connecting between the bottom electrode layer and the first external electrode, the connection conductor including a first contact portion contacting the substrate.

A light receiving device (3) includes a first circuit substrate (10) and a second circuit substrate (20). An avalanche photodiode (APD) (101) and a protection element (130) that protects the APD (101) are disposed on the first circuit substrate (10). The second circuit substrate (20) is stacked on the first circuit substrate (10), and a signal processing circuit that processes a signal output from the APD (101) is disposed on the second circuit substrate (20).

A semiconductor device is provided that includes a substrate 10 with first and second opposing main surfaces, a circuit layer disposed on the first main surface, and a first resin body on a surface of the circuit layer opposite from the substrate. The circuit layer includes first and second electrode layers on a side of the semiconductor substrate, a dielectric layer disposed between the electrode layers, a first outer electrode electrically connected to the first electrode layer and extended to the surface of the circuit layer, and a second outer electrode electrically connected to the second electrode layer and extended to the surface of the circuit layer. The first resin body is between the first and second outer electrodes in a plan view, and in sectional view, a tip end of the first resin body is positioned higher than tip ends of the first and second outer electrodes.

A capacitor according to an embodiment includes a substrate having a first surface and a second surface and provided with one or more first through holes each extending from the first surface to the second surface, a first conductive layer covering the first surface, the second surface, and side walls of the one or more first through holes, a second conductive layer facing the first surface, the second surface, and the side walls of the one or more first through holes, with the first conductive layer interposed therebetween, and a dielectric layer interposed between the first conductive layer and the second conductive layer.

A semiconductor device is provided having a semiconductor substrate with a circuit layer provided on a first main surface of the semiconductor substrate. The circuit layer includes a first and second electrode layers with a dielectric layer disposed therebetween, a first outer electrode electrically connected to the first electrode layer and a second outer electrode electrically connected to the second electrode layer. When the circuit layer is viewed from above, the first electrode layer has a first facing portion facing the second electrode layer in the thickness direction and a first non-facing portion not facing the second electrode layer, and the second electrode layer has a second facing portion facing the first electrode layer in the thickness direction and a second non-facing portion not facing the first electrode layer.

Systems, devices and methods of manufacturing a system on silicon wafer (SoSW) device and package are described herein. A plurality of functional dies is formed in a silicon wafer. Different sets of masks are used to form different types of the functional dies in the silicon wafer. A first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. A second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. An optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. The optional backside redistribution structure may provide backside interconnects between functional dies of different types.

According to one embodiment, a display device includes a display area where a plurality of pixels are arrayed, a first drive circuit arranged adjacent to the display area in a first direction, the first drive circuit configured to supply a drive signal to a gate electrode included in each of switching elements, and a memory power line extending in a second direction intersecting the first direction in the display area and configured to supply a potential to a memories. An outer edge of the display area is defined by outermost edges of the pixels located on an outermost side in the display area. A first distance from the first drive circuit to the outer edge is shorter than a second distance from the first drive circuit to the memory power line.

A capacitor that includes a substrate, a lower electrode on the substrate, a dielectric film on the lower electrode, an upper electrode on a part of the dielectric film, a protective layer that covers the lower electrode and the upper electrode, and an external electrode that penetrates the protective layer. The external electrode is formed only in a region defined by a periphery of the upper electrode in a plan view of the capacitor viewed from an upper surface thereof towards the substrate.