Disclosed are a method and a device for manufacturing an array substrate, and an array substrate. The method includes: depositing and forming a gate insulation layer on a pre-formed base substrate and a pre-formed gate, the gate insulation layer covering the pre-formed gate; depositing and forming an amorphous silicon layer, a doped amorphous silicon layer including at least three doped layers, and a metal layer on the gate insulation layer in sequence, doping concentrations of the at least three doped layers of the doped amorphous silicon layer increasing from bottom to top; etching patterns of the amorphous silicon layer, the doped amorphous silicon layer and the metal layer to form the array substrate.

A display device includes a pixel connected to a data line, a data pad connected to the data line, and a first test area. The first test area includes a test control line transmitting a test control signal, a test signal line transmitting a test signal, and a first switch connected to the data pad. The first switch includes a gate electrode connected to the test control line, first and second semiconductor layers overlapping the gate electrode, a source electrode connected to the first and second semiconductor layers, and a drain electrode spaced from the source electrode and connected to the first and second semiconductor layers. The source electrode and the drain electrode are connected to the test signal line and data pad, respectively. One of the first or second semiconductor layers includes an oxide semiconductor and the other of the first or second semiconductor layer includes a silicon-based semiconductor.

A glass substrate has a compaction of 0.1 to 100 ppm. An absolute value |Δα.sub.50/100| of a difference between an average coefficient of thermal expansion α.sub.50/100 of the glass substrate and an average coefficient of thermal expansion of single-crystal silicon at 50° C. to 100° C., an absolute value |Δα.sub.100/200| of a difference between an average coefficient of thermal expansion α.sub.100/200 of the glass substrate and an average coefficient of thermal expansion of the single-crystal silicon at 100° C. to 200° C., and an absolute value |Δα.sub.200/300| of a difference between an average coefficient of thermal expansion α.sub.200/300 of the glass substrate and an average coefficient of thermal expansion of the single-crystal silicon at 200° C. to 300° C. are 0.16 ppm/° C. or less.

A glass substrate has a compaction of 0.1 to 100 ppm. An absolute value |Δα.sub.50/100| of a difference between an average coefficient of thermal expansion α.sub.50/100 of the glass substrate and an average coefficient of thermal expansion of single-crystal silicon at 50° C. to 100° C., an absolute value |Δα.sub.100/200| of a difference between an average coefficient of thermal expansion α.sub.100/200 of the glass substrate and an average coefficient of thermal expansion of the single-crystal silicon at 100° C. to 200° C., and an absolute value |Δα.sub.200/300| of a difference between an average coefficient of thermal expansion α.sub.200/300 of the glass substrate and an average coefficient of thermal expansion of the single-crystal silicon at 200° C. to 300° C. are 0.16 ppm/° C. or less.

A metal structure includes a patterned molybdenum tantalum oxide layer and a patterned metal layer. The patterned molybdenum tantalum oxide layer is disposed on a first substrate, in which the patterned molybdenum tantalum oxide layer includes about 2 to 12 atomic percent of tantalum. Both of an atomic percent of molybdenum and an atomic percent of oxygen of the patterned molybdenum tantalum oxide layer are greater than the atomic percent of tantalum of the patterned molybdenum tantalum oxide layer. The patterned metal layer is disposed on the patterned molybdenum tantalum oxide layer.

Proposed is a method for manufacturing a micro LED display, the method including a step of preparing a plurality of first substrates having a plurality of micro LEDs, respectively, a step of preparing a plurality of second substrates, a segmented region formation step of segmenting each of the first substrates into a plurality of regions, and a step of transferring micro LEDs of one segmented region of each of the first substrates to an associated one of the second substrates, wherein the one second substrate comprises the micro LEDs of the first substrate.

This disclosure is related to arranging to a system comprising of backplane and micro-devices. The backplane components layers may comprise of multiple conductive layers and multiple dielectric or semiconductor layers. The system is a stacked structure The stacking structure can be used with different types of transistors and backplane including but not limited to staggered, inverted staggered, and other types In addition, touch sensing structure can be integrated into the system.

According to one embodiment, a semiconductor device includes a first transistor which includes a an oxide semiconductor layer, and a second transistor connected to first and a second gate electrodes of the first transistor, wherein the oxide semiconductor layer is provided between the first and second gate electrodes in a cross-sectional view, the oxide semiconductor layer includes a first channel formation region overlapping the second gate electrode and a second channel formation region not overlapping the second gate electrode in a plan view, and a resistance value between the second gate electrode and the second transistor is higher than a resistance value between the first gate electrode and the second transistor.

To suppress degradation of a transistor. A method for driving a liquid crystal display device has a first period and a second period. In the first period, a first transistor and a second transistor are alternately turned on and off repeatedly, and a third transistor and a fourth transistor are turned off. In the second period, the first transistor and the second transistor are turned off, and the third transistor and the fourth transistor are alternately turned on and off repeatedly. Accordingly, the time during which the transistor is on can be reduced, so that degradation of characteristics of the transistor can be suppressed.

The present disclosure provides a display device comprising: a first thin film transistor including a first semiconductor pattern disposed on a substrate and comprising poly-silicon, and a first gate electrode; a middle layer on the first gate electrode; a second thin film transistor including a second semiconductor pattern disposed on the middle layer and comprising an oxide semiconductor, and a second gate electrode; and a storage capacitor including first to fourth storage electrodes overlapping with each other.