A semiconductor device according to the present disclosure includes: a gate electrode provided in a gate trench and provided so as to oppose a source region via a gate insulating film; a first bottom protection region of a second conductivity type provided below the gate insulating film; a plurality of first connection regions of the second conductivity type provided at a first interval in an extension direction of the gate trench and electrically connecting the first bottom protection region and a body region; a Schottky electrode provided in a Schottky trench; a second bottom protection region of the second conductivity type provided below the Schottky electrode; and a plurality of second connection regions of the second conductivity type provided at a second interval smaller than the first interval in an extension direction of the Schottky trench and electrically connecting the second bottom protection region and the body region.

The disclosure discloses an array substrate, an OLED display panel and a display device. A storage capacitor includes a first capacitor and a second capacitor which are connected in parallel, wherein the first capacitor includes a storage electrode and a first electrode, a layer where the first electrode is located is same as a layer where the grid electrode of the driving transistor is located, the second capacitor includes the storage electrode and a second electrode, a layer where the second electrode is located is same as a layer where the power supply voltage line is located, and the first electrode and the second electrode are electrically connected through a via hole penetrating through a first insulating layer and a second insulating layer.

An in-memory computing architecture is disclosed that can evaluate the transitive closure of graphs using the natural parallel flow of information in 3-D nanoscale crossbars. The architecture can be implemented using 3-D crossbar architectures with as few as two layers of 1-diode 1-resistor (1D1R) interconnects. The architecture avoids memory-processor bottlenecks and can hence scale to large graphs. The approach leads to a runtime complexity of O(n.sup.2) using O(n.sup.2) memristor devices. This compares favorably to conventional algorithms with a time complexity of O((n.sup.3)/p+(n.sup.2) log p) on p processors. The approach takes advantage of the dynamics of 3-D crossbars not available on 2-D crossbars.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a plurality of gates disposed above the quantum well stack, wherein at least two of the gates are spaced apart in a first dimension above the quantum well stack, at least two of the gates are spaced apart in a second dimension above the quantum well stack, and the first and second dimensions are perpendicular; and an insulating material disposed above the quantum well stack, wherein the insulating material extends between at least two of the gates spaced apart in the first dimension, and the insulating material extends between at least two of the gates spaced apart in the second dimension.

A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film. The signal line intersects with the scan line, the first electrode is electrically connected to the signal line, the first electrode has a region overlapping with the scan line, the second electrode faces the first electrode, the third electrode faces the first electrode, the first pixel electrode is electrically connected to the second electrode, the second pixel electrode is electrically connected to the third electrode, the semiconductor film is in contact with the first electrode, the second electrode, and the third electrode, and the semiconductor film is provided between the scan line and the first electrode to the third electrode.

A quantum wire device includes a barrier formed by an insulator or a wide bandgap semiconductor, and metal quantum wires comprising a metal material and embedded in the barrier. Potential wells are formed for electrons in the metal quantum wires by the insulator or the wide bandgap semiconductor. The work function of the metal quantum wires is reduced by quantum confinement compared to a bulk form of the metal material. The metal quantum wires are electrically connected. The metal quantum wires include an exposed active area for electron emission or electron collection.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a plurality of gates disposed on the quantum well stack; and a top gate at least partially disposed on the plurality of gates such that the plurality of gates are at least partially disposed between the top gate and the quantum well stack.

A battery management circuit, a battery protection circuit, a power storage device, a semiconductor device, a vehicle, and an electronic device, or the like with a novel structure, a low power consumption structure, or a highly integrated structure is provided. The semiconductor device includes a first transistor comprising a first conductor and a first semiconductor over the first conductor, a first insulator over the first transistor, a second conductor provided in an opening of the first insulator, a second transistor over the first insulator, and a third conductor over the second transistor. The first conductor has a function of one of a source electrode and a drain electrode of the first transistor. The first semiconductor and the second conductor overlap each other. The second conductor and the third conductor overlap each other. The third conductor and the second transistor overlap each other. The first semiconductor and the second transistor are electrically connected to each other through the second conductor and the third conductor.

A semiconductor device, including a semiconductor substrate, a transistor section and a diode section arranged in a predetermined arrangement direction and provided on the semiconductor substrate, is provided. The diode section includes a drift region of a first conductivity-type provided in the semiconductor substrate, a base region of a second conductivity-type extending to a height of an upper surface of the semiconductor substrate and provided above the drift region, first cathode regions of the first conductivity-type, and second and third cathode regions of the second conductivity-type. The first, second, and third cathode regions extend to a height of a lower surface of the semiconductor substrate in a depth direction and provided below the drift region. The first and second cathode regions are provided in contact with each other, alternating in the arrangement direction, and sandwiched between the third cathode regions in an extension direction orthogonal to the arrangement direction.

A semiconductor device having a GeSiSn base region combined with an emitter region and a collector region can be used to fabricate a bipolar transistor or a heterojunction bipolar transistor. The GeSiSn base region can be compositionally graded or latticed matched or strained to GaAs. The GeSiSn base region can be wafer bonded to a GaN or SiC collector region.