There is provided a semiconductor device comprising: a semiconductor substrate including a drift region of a first conductivity type; an emitter region of the first conductivity type provided above the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region; a base region of a second conductivity type provided between the emitter region and the drift region inside the semiconductor substrate; a first accumulation region of the first conductivity type provided between the base region and the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region; a plurality of trench portions provided to pass through the emitter region, the base region and first accumulation region from an upper surface of the semiconductor substrate, and provided with a conductive portion inside; and a capacitance addition portion provided below the first accumulation region to add a gate-collector capacitance thereto.

A transparent display device is disclosed, which may prevent a short circuit from occurring between first and second capacitor electrodes of a capacitor. The transparent display device includes a substrate provided with a display area including a transmissive area and a non-transmissive area, in which a plurality of subpixels are disposed, and a non-display area adjacent to the display area, a driving transistor provided in the non-transmissive area over the substrate, including an active layer, a gate electrode, a source electrode and a drain electrode, and a capacitor provided in the non-transmissive area over the substrate, including a first capacitor electrode and a second capacitor electrode. The second capacitor electrode is not overlapped with the active layer of the driving transistor.

The present techniques relate to a semiconductor device having resistance which has a positive temperature coefficient and a suitable value, and to a method for manufacturing a semiconductor device having resistance which has a positive temperature coefficient and a suitable value. The semiconductor device related to the present techniques is a bipolar device in which a current flows through a pn junction. The semiconductor device includes an n-type silicon carbide drift layer, a p-type first silicon carbide layer formed on the silicon carbide drift layer, and a p-type second silicon carbide layer formed on the first silicon carbide layer. Then, the second silicon carbide layer has a positive temperature coefficient of resistance.

Using processes disclosed herein, materials and structures are created and used. For example, processes can include melting amorphous carbon doped with nitrogen and carbon-13 into an undercooled state followed by quenching. Materials disclosed herein may include dopants in concentrations exceeding thermodynamic solubility limits.

It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.

It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.

On a front surface of an n.sup.+-type SiC substrate becoming a drain region, an n.sup.−-type drift layer, a p-type base layer, and an n.sup.+-type source layer are sequentially formed by epitaxial growth. In the n.sup.+-type source layer, the p.sup.+-type contact region is selectively provided. A trench is provided penetrating the n.sup.+-type source layer and the p-type base layer in the depth direction and reaching the n.sup.−-type drift layer. In the trench, a gate electrode is provided via a gate insulating film. A width between adjacent trenches is, for example, 1 μm or less. A depth of the trench is, for example, 1 μm or less. The width is narrow whereby substantially the entire p-type base layer forms a channel. A cell includes a FinFET structure in which one channel is sandwiched between MOS gates on both side. Thus, ON resistance may be reduced and decreased reliability may be prevented.

To realize a highly reliable IGBT that suppresses the bipolar degradation by preventing the occurrence of a defect on a boundary between a contact region and a silicide layer. As a means to realize the above, a semiconductor device includes: a collector region that is formed on a lower surface of a semiconductor substrate and forms an IGBT; and a collector electrode that is formed on a lower surface of the collector region via a silicide layer. The collector region and the silicide layer contains aluminum, first metal being more easily bondable to silicon than aluminum, and second metal being more easily bondable to carbon than aluminum.

A method for determining an optimal spin/charge conversion operating point in a system including a pair of quantum dots including first and second quantum dots, the pair of quantum dots containing two charged particles and adopting a first charge state (2,0) in which both charged particles are in the first quantum dot, a second charge state (1,1) in which each quantum dot contains a charged particle, or a third charge state (0,2) in which both charged particles are in the second quantum dot, the charge state being a function of the voltage applied to at least two gates, the value of these voltages defining an operating point of the pair of quantum dots; the charged particles adopting a first spin state, called singlet spin state S, or a second spin state, called triplet spin state among the triplet spin state T0 or the triplet spin state T+/T−.

An integrated circuit die includes a quad-gate device nanowire of channel material for a transistor (e.g., single material or stack to be a channel of a MOS device) formed by removing a portion of a sub-fin material from below the channel material, where the sub-fin material was grown in an aspect ration trapping (ART) trench. In some cases, in the formation of such nanowires, it is possible to remove the defective fin material or area under the channel. Such removal isolates the fin channel, removes the fin defects and leakage paths, and forms the nanowire of channel material having four exposed surfaces upon which gate material may be formed.