A method for manufacturing nitride semiconductor device includes a second step of forming, on a gate layer material film, a gate electrode film that is a material film of a gate electrode, a third step of selectively etching the gate electrode film to form the gate electrode 22 of a ridge shape, and a fourth step of selectively etching the gate layer material film to form a semiconductor gate layer 21 of a ridge shape with the gate electrode 22 disposed at a width intermediate portion of a front surface thereof. The third step includes a first etching step for forming a first portion 22A from an upper end to a thickness direction intermediate portion of the gate electrode 22 and a second etching step being a step differing in etching condition from the first etching step and being for forming a remaining second portion 22B of the gate electrode.

A nitride semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer, a third nitride semiconductor layer that is disposed on the second nitride semiconductor layer, has a ridge portion at least at a portion thereof, and contains an acceptor type impurity, a gate electrode that is disposed on the ridge portion, and a source electrode and a drain electrode that, on the second nitride semiconductor layer, are disposed across the ridge portion from each other, and has an active region and a nonactive region. The nonactive region has a first region and a film thickness of the second nitride semiconductor layer in the first region differs from a film thickness of the second nitride semiconductor layer in a region of the active region in which the ridge portion, the source electrode, and the drain electrode are not formed.

Integrated semiconductor devices and method of making the integrated semiconductor are disclosed. The integrated semiconductor device may include a first transistor comprising a first gate and at least one first active region, a second transistor comprising a second gate and at least one second active region, wherein the second transistor is spaced a first distance from the first transistor, a dielectric sidewall spacer formed on a gate sidewall of the first transistor and a gate sidewall of the second transistor, a first dielectric layer formed over the first transistor and the second transistor, wherein a thickness of the first dielectric layer is greater than half the first distance, and a patterned metal layer formed on the first dielectric layer and partially covering the second gate.

The structure and technology to improve the device performance of III-nitride semiconductor transistors at high drain voltage when the device is off is disclosed. P-type semiconductor regions are disposed between the gate electrode and the drain contact of the transistor structure. The P-type regions are electrically connected to the drain electrode. In some embodiments, the P-type regions are physically contacting the drain contact. In other embodiments, the P-type regions are physically separate from the drain contact, but electrically connected to the drain contact.

A semiconductor device includes: a substrate (10); a semiconductor layer (20) disposed on a main surface of this substrate (10); and a first main electrode (30) and a second main electrode (40), which are disposed on the substrate (10) separately from each other with the semiconductor layer (20) sandwiched therebetween and are individually end portions of a current path of a main current flowing in an on-state. The semiconductor layer (20) includes: a first conductivity-type drift region (21) through which a main current flows; a second conductivity-type column region (22) that is disposed inside the drift region (21) and extends in parallel to a current path; and an electric field relaxation region (23) that is disposed in at least a part between the drift region (21) and the column region (22) and is either a low-concentration region in which an impurity concentration is lower than in the same conductivity-type adjacent region or a non-doped region.

The present disclosure provides a nitride semiconductor device. The nitride semiconductor device includes: an electron transport layer, made of a nitride semiconductor; an electron supply layer, disposed on the electron transport layer and made of a nitride semiconductor having a band gap greater than a band gap of the nitride semiconductor of the electron transport layer; a first protective layer, disposed on the electron supply layer and made of a nitride semiconductor having a band gap less than the band gap of the nitride semiconductor of the electron supply layer; a second protective layer, disposed on a portion of the first protective layer and made of a nitride semiconductor having a band gap greater than the band gap of the nitride semiconductor of the first protective layer; and a gate layer, disposed on the second protective layer.

A semiconductor device includes: an n type semiconductor layer including an active region and an inactive region; an element structure formed in the active region and including at least an active side p type layer to form pn junction with n type portion of the n type semiconductor layer; an inactive side p type layer formed in the inactive region and forming pn junction with the n type portion of the n type semiconductor layer; a first electrode electrically connected to the active side p type layer in a front surface of the n type semiconductor layer; a second electrode electrically connected to the n type portion of the n type semiconductor layer in a rear surface of the n type semiconductor layer; and a crystal defect region formed in both the active region and the inactive region and having different depths in the active region and the inactive region.

A semiconductor device having a voltage resistant structure in a first aspect of the present invention is provided, comprising a semiconductor substrate, a semiconductor layer on the semiconductor substrate, a front surface electrode above the semiconductor layer, a rear surface electrode below the semiconductor substrate, an extension section provided to a side surface of the semiconductor substrate, and a resistance section electrically connected to the front surface electrode and the rear surface electrode. The extension section may have a lower permittivity than the semiconductor substrate. The resistance section may be provided to at least one of the upper surface and the side surface of the extension section.

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

In one embodiment, the semiconductor devices relate to using one or more super-junction trenches for termination.