SEMICONDUCTOR DEVICE INCLUDING CRYSTAL DEFECT REGION AND METHOD FOR MANUFACTURING THE SAME

Abstract

A semiconductor device includes: an n type semiconductor layer including an active region and an inactive region; an element structure formed in the active region and including at least an active side p type layer to form pn junction with n type portion of the n type semiconductor layer; an inactive side p type layer formed in the inactive region and forming pn junction with the n type portion of the n type semiconductor layer; a first electrode electrically connected to the active side p type layer in a front surface of the n type semiconductor layer; a second electrode electrically connected to the n type portion of the n type semiconductor layer in a rear surface of the n type semiconductor layer; and a crystal defect region formed in both the active region and the inactive region and having different depths in the active region and the inactive region.

Claims

1. A semiconductor device comprising: a first conductivity type semiconductor layer including an active region and an inactive region; an element structure which is formed in the active region and includes at least an active side second conductivity type layer to form a pn junction with a first conductivity type portion of the first conductivity type semiconductor layer; an inactive side second conductivity type layer which is formed in the inactive region and forms a pn junction with the first conductivity type portion of the first conductivity type semiconductor layer; a first electrode which is electrically connected to the active side second conductivity type layer in a front surface of the first conductivity type semiconductor layer; a second electrode which is electrically connected to the first conductivity type portion of the first conductivity type semiconductor layer in a rear surface of the first conductivity type semiconductor layer; and a crystal defect region which is formed in both of the active region and the inactive region, the crystal defect region in the active region being at a first depth within the first conductivity type portion and the crystal defect region in the inactive region being at a second depth within the first conductivity type portion, and the second depth being different from the first depth.

2. The semiconductor device of claim 1, wherein the crystal defect region in the active region is formed in the vicinity of a bottom of the active side second conductivity type layer, and wherein the crystal defect region in the inactive region is formed to be separated from a bottom of the inactive side second conductivity type layer such that the crystal defect region of the inactive region is closer to the rear surface of the first conductivity type semiconductor layer than the bottom of the inactive side second conductivity type layer.

3. The semiconductor device of claim 2, wherein a distance between the crystal defect region in the active region and the bottom of the active side second conductivity type layer is 5 μm or less, and wherein a distance between the crystal defect region in the inactive region and the bottom of the inactive side second conductivity type layer is 5 μm or more.

4. The semiconductor device of claim 1, wherein the active side second conductivity type layer and the inactive side second conductivity type layer have the same thickness.

5. The semiconductor device of claim 1, wherein the element structure includes: a first conductivity type base layer; a second conductivity type base layer which is partially formed on a surficial layer portion of the first conductivity type base layer in the active region; a first conductivity type source layer which is partially formed on the surficial layer portion of the first conductivity type base layer in the active region; a gate insulating film which is formed on a front surface of the second conductivity type base layer between the first conductivity type source layer and the first conductivity type base layer; and a gate electrode on the gate insulating film, the gate electrode facing the first conductivity type source layer and the second conductivity type base layer via the gate insulating film, and wherein the active side second conductivity type layer includes an active side second conductivity type column layer, which is formed in the first conductivity type base layer to be continuous to the second conductivity type base layer, and which extends from a front surface of the first conductivity type base layer to a rear surface of the first conductivity type base layer.

6. The semiconductor device of claim 5, wherein the inactive side second conductivity type layer includes a second conductivity type guard ring surrounding the active region.

7. The semiconductor device of claim 6, wherein a depth of the second conductivity type guard ring is equal to a depth of the second conductivity type column layer.

8. The semiconductor device of claim 5, wherein the crystal defect region in the active region is formed near the second conductivity type column layer.

9. The semiconductor device of claim 6, wherein the inactive side second conductivity type layer further includes an inactive side second conductivity type column layer, wherein a distance between the crystal defect region in the active region and a bottom of the active side second conductivity type column layer is 5 μm or less, and wherein a distance between the crystal defect region in the inactive region and a bottom of the inactive side second conductivity type column layer is 10 μm or more.

10. A method for manufacturing a semiconductor device, comprising: forming an element structure including at least an active side second conductivity type layer to form a pn junction with a first conductivity type portion of a first conductivity type semiconductor layer including an active region and an inactive region, in the active region of the first conductivity type semiconductor layer; forming an inactive side second conductivity type layer to form a pn junction with the first conductivity type portion of the first conductivity type semiconductor layer, in the inactive region; forming a level difference on the rear surface of the first conductivity type semiconductor layer between the active region and the inactive region such that a level of the active region is lower than a level of the inactive region; irradiating charged particles over the entire rear surface of the first conductivity type semiconductor layer after forming the level difference to form a crystal defect region which is formed in both of the active region and the inactive region, the crystal defect region in the active region being at a first depth within the first conductivity type portion and the crystal defect region in the inactive region being at a second depth within the first conductivity type portion, and the second depth being different from the first depth; forming a first electrode to be electrically connected to the active side second conductivity type layer in a front surface of the first conductivity type semiconductor layer; and forming a second electrode to be electrically connected to the first conductivity type portion of the first conductivity type semiconductor layer in the rear surface of the first conductivity type semiconductor layer.

11. The method of claim 10, wherein the act of forming the level difference includes: forming a mask having an opening on the active region, in the rear surface of the first conductivity type semiconductor layer; and forming a concave portion in the first conductivity type semiconductor layer by deep-etching the active region through the mask.

12. The method of claim 11, further comprising: after irradiating the charged particles, grinding and flattening the rear surface of the first conductivity type semiconductor layer.

13. The method of claim 10, wherein the act of forming the level difference includes: forming a first mask on the entire rear surface of the first conductivity type semiconductor layer; forming a second mask having an opening on the active region, on the first mask; and forming a level difference between the rear surface of the first conductivity type semiconductor layer and the remaining portion of the first mask by etching the first mask through the second mask.

14. The method of claim 10, further comprising: activating the crystal defect region with charged particles implanted into the first conductivity type semiconductor layer by subjecting the first conductivity type semiconductor layer to a heat treatment at a predetermined first temperature.

15. The method of claim 14, wherein the first temperature is 320 degrees C. to 380 degrees C.

16. The method of claim 14, further comprising: after subjecting the first conductivity type semiconductor layer to the heat treatment, forming a rear surface contact by implanting first conductivity type impurity ions into the rear surface of the first conductivity type semiconductor layer and activating an implantation portion of the first conductivity type impurity ions by the heat treatment using laser annealing.

17. The method of claim 10, wherein the charged particles include one of proton .sup.3He.sup.++ and proton .sup.4He.sup.++.

18. The method of claim 10, wherein the element structure includes: a first conductivity type base layer; a second conductivity type base layer which is partially formed on a surficial layer portion of the first conductivity type base layer in the active region; a first conductivity type source layer which is partially formed on the surficial layer portion of the first conductivity type base layer in the active region; a gate insulating film which is formed on a front surface of the second conductivity type base layer between the first conductivity type source layer and the first conductivity type base layer; and a gate electrode on the gate insulating film, the gate electrode facing the first conductivity type source layer and the second conductivity type base layer via the gate insulating film, and wherein the active side second conductivity type layer includes a second conductivity type column layer which is formed in the first conductivity type base layer to be continuous to the second conductivity type base layer and extends from a front surface of the first conductivity type base layer to a rear surface of the first conductivity type base layer.

19. The method of claim 18, wherein the inactive side second conductivity type layer includes a second conductivity type guard ring surrounding the active region.

20. The method of claim 19, wherein the second conductivity type guard ring has the same depth as the second conductivity type column layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG. 1 is a schematic plan view of a semiconductor device according to one embodiment of the present disclosure.

[0021] FIG. 2 is a sectional view illustrating main parts of the semiconductor device.

[0022] FIG. 3A is a view illustrating a step in a process of manufacturing the semiconductor device.

[0023] FIG. 3B is a view illustrating a step subsequent to the step of FIG. 3A.

[0024] FIG. 3C is a view illustrating a step subsequent to the step of FIG. 3B.

[0025] FIG. 3D is a view illustrating a step subsequent to the step of FIG. 3C.

[0026] FIG. 3E is a view illustrating a step subsequent to the step of FIG. 3D.

[0027] FIG. 4A is a view illustrating a step in a process of manufacturing the semiconductor device.

[0028] FIG. 4B is a view illustrating a step subsequent to the step of FIG. 4A.

[0029] FIG. 4C is a view illustrating a step subsequent to the step of FIG. 4B.

[0030] FIG. 4D is a view illustrating a step subsequent to the step of FIG. 4C.

[0031] FIG. 4E is a view illustrating a step subsequent to the step of FIG. 4D.

[0032] FIG. 5 is a graph showing results of verification on a variation in peak breakdown voltage with respect to an ion stop position.

[0033] FIG. 6 is a graph showing results of verification on a variation in peak breakdown voltage with respect to an ion stop position.

[0034] FIG. 7 is a graph showing results of verification on a variation in peak breakdown voltage with respect to an ion stop position.

[0035] FIG. 8 is a graph showing results of verification on a variation in peak breakdown voltage with respect to an ion stop position.

[0036] FIG. 9 is a view illustrating an irradiation pattern used for verification on an effect obtained by masking a peripheral field region.

[0037] FIG. 10 is a graph showing results of verification on a variation in breakdown voltage before and after irradiation of .sup.3He.sup.++ ions.

[0038] FIG. 11 is a graph showing results of verification on a variation in breakdown voltage before and after irradiation of .sup.3He.sup.++ ions.

[0039] FIG. 12 is a graph showing results of verification on a variation in breakdown voltage before and after irradiation of .sup.3He.sup.++ ions.

[0040] FIG. 13 is a graph showing results of verification on a variation in breakdown voltage before and after irradiation of .sup.3He.sup.++ ions.

DETAILED DESCRIPTION

[0041] Some embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0042] FIG. 1 is a schematic plan view of a semiconductor device 1 according to one embodiment of the present disclosure. The semiconductor device 1 includes a semiconductor substrate 2 as one example of an n type semiconductor layer of the present disclosure. The semiconductor substrate 2 may be a Si substrate or other substrate used for a power device, such as a SiC substrate, a GaN substrate or the like. As shown in FIG. 1, the semiconductor substrate 2 may be rectangular, when viewed from top.

[0043] An active region 3 and an inactive region 4 surrounding the active region 3 are defined on the semiconductor substrate 2. The inactive region 4 may include a gate pad region 5 and a peripheral field region 6. The active region 3, the gate pad region 5 and the peripheral field region 6 are regions surrounded by thick broken lines, respectively, in FIG. 1. The peripheral field region 6 is formed in an annular shape along the periphery of the semiconductor substrate 2 and the active region 3 and the gate pad region 5 are defined in the inner region of the peripheral field region 6. The gate pad region 5 protrudes inward from the inner periphery of the peripheral field region 6.

[0044] An electrode film 7 is formed on the semiconductor substrate 2. The electrode film 7 is made of, e.g., aluminum or other metal. The electrode film 7 may include a source pad 8 on the active region 3, as one example of a first electrode of the present disclosure, a gate pad 9 on the gate pad region 5, and a field plate 10 on the peripheral field region 6. The source pad 8, the gate pad 9 and the field plate 10 are separated and electrically isolated from each other. A peripheral portion of the source pad 8 may be disposed in the side of the peripheral field region 6 from an interface (indicated by a thick broken line) between the active region 3 and the peripheral field region 6, as shown in FIG. 1. Thus, a portion of the source pad 8 is disposed above a p type guard ring 11 formed in the peripheral field region 6.

[0045] FIG. 2 is a sectional view illustrating main parts of the semiconductor device 1. FIG. 2 is also a schematic view for explaining the sectional structure of the semiconductor device 1 in detail but does not depict a cut section at a particular position of the semiconductor device 1 of FIG. 1. The semiconductor device 1 is an n channel type MISFET having a super junction structure. More specifically, the semiconductor device 1 includes an n.sup.+ type drain layer 12, an n type base layer 13 as one example of an n type portion of the present disclosure, a p type column layer 14 and p type base layer 15 as one example of an active side p type layer of the present disclosure, an n.sup.+ type source layer 16, a gate insulating film 17, a gate electrode 18, a p type guard ring 11 as one example of an inactive side p type layer of the present disclosure, a field insulating film 19, a field embedded electrode 20, an interlayer insulating film 21, a source pad 8, a field plate 10, a drain electrode 22 as one example of a second electrode of the present disclosure, and a crystal defect region 23.

[0046] The n.sup.+ type drain layer 12 may be formed from an n.sup.+ type semiconductor substrate (e.g., a silicon substrate). The n.sup.+ type semiconductor substrate may be a semiconductor substrate in which crystals are grown while being doped with n type impurities such as phosphorus (P), arsenic (As), antimony (Sb) or the like. The n.sup.+ type drain layer 12 may have a thickness of, e.g., 90 μm to 310 μm.

[0047] The n type base layer 13 may be a semiconductor layer doped with n type impurities, more specifically, an n type epitaxial layer epitaxial-grown while being doped with the n type impurities. As the n type impurities, the n type impurities as described above may be used. In other words, the semiconductor substrate 2 of FIG. 1 may be an epitaxial substrate including the n.sup.+ type drain layer 12 (a base substrate) and the n type base layer 13 (an epitaxial layer) formed thereon. The n type base layer 13 may have a thickness of, e.g., 40 μm to 60 μm. Therefore, the total thickness of the semiconductor substrate 2 including the n.sup.+ type drain layer 12 and the n type base layer 13 may be, e.g., 150 μm to 350 μm.

[0048] The p type column layer 14 and the p type base layer 15 may be a semiconductor layer doped with p type impurities, more specifically, a semiconductor layer formed by implanting ions of p type impurities such as boron (B), aluminum (Al), gallium (Ga) or the like into the n type base layer 13. The p type base layer 15 may be selectively formed on a surficial layer portion of the n type base layer 13 in a plurality of regions which are discretely arranged periodically in plan view of the semiconductor device 1. A region including each p type base layer 15 and an n type base layer 13 therearound may form a unit cell 24. The semiconductor device 1 may have a number (plurality) of unit cells 24 arranged in the form of a lattice in plan view of the semiconductor device 1.

[0049] The p type column layer 14 may be formed in an inner region of the p type base layer 15 of each unit cell 24 in plan view. More specifically, the p type column layer 14 may be formed in a shape, e.g., similar to the shape of the p type base layer 15 in substantially the central region of the p type base layer 15 when viewed from top. The p type column layer 14 is formed so as to be continuous to the p type base layer 15 and may extend toward the n.sup.+ type drain layer 12 up to a position deeper than the p type base layer 15 in the n type base layer 13. In other words, the p type column layer 14 may be formed substantially in a columnar shape. In addition, the shape of the p type column layer 14 is not limited to the columnar shape but may have, e.g., a stripe shape when viewed from top. The bottom 14a of the p type column layer 14 may be located at a position nearer to the n.sup.+ type drain layer 12 than the center in the thickness direction of the n type base layer 13. The depth of the p type column layer 14 may be smaller by about 15 μm than the thickness of the n type base layer 13, for example, 25 μm to 45 μm. The bottom 14a of the p type column layer 14 (an interface with the n type base layer 13) faces the front surface (the upper surface in FIG. 2) of the n.sup.+ type drain layer 12 with the n type base layer 13 sandwiched therebetween in the thickness direction. In addition, a side 14b of the p type column layer 14 (an interface with the n type base layer 13) faces a side 14b of another adjacent p type column layer 14 with the n type base layer 13 sandwiched therebetween.

[0050] An interface between the n type base layer 13 and the p type base layer 15 and the p type column layer 14 is a pn junction and forms a parasitic diode (body diode) 25. The n.sup.+ type source layer 16 may be formed in the inner region of the p type base layer 15 of each unit cell 24. The n.sup.+ type source layer 16 may be selectively formed on a surficial layer portion of the p type base layer 15 in the corresponding region. The n.sup.+ type source layer 16 may be formed by selectively implanting ions of the n type impurities into the p type base layer 15. The n type impurities may be the n type impurities as described above. The n.sup.+ type source layer 16 is formed within the p type base layer 15 so as to be positioned inward by a predetermined distance from an interface between the p type base layer 15 and the n type base layer 13. Thus, in a surficial layer region of the semiconductor layer including the n type base layer 13, the p type base layer 15 and so on, the surficial layer portion of the p type base layer 15 is interposed between the n.sup.+ type source layer 16 and the n type base layer 13. The interposed surficial layer portion forms a channel region 26. The n.sup.+ type source layer 16 may be formed in a region extending from the inside to the outside of the side 14b of the p type column layer 14.

[0051] The gate insulating film 17 may be formed of, e.g., a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a hafnium oxide film, an alumina film or a tantalum oxide film. The gate insulating film 17 is formed so as to cover the front surface of the p type base layer 15 at least in the channel region 26. In this embodiment, the gate insulating film 17 is formed so as to cover a portion of the n.sup.+ type source layer 16, the channel region 26 and the front surface of the n type base layer 13. More plainly, the gate insulating film 17 is formed in a pattern having an opening in the central region of the p type base layer 15 in each unit cell 24 and the inner edge region of the n+ type source layer 16 continuous to the central region. The gate insulating film 17 may have a thickness of, e.g., 0.005 μm to 0.03 μm.

[0052] The gate electrode 18 is formed so as to face the channel region 26 via the gate insulating film 17. The gate electrode 18 may be made of, e.g., polysilicon having resistance decreased by being doped with impurities. In this embodiment, the gate electrode 18 is formed in substantially the same pattern as the gate insulating film 17 and covers the front surface of the gate insulating film 17. In other words, the gate electrode 18 is disposed above a portion of the n.sup.+ type source layer 16, the channel region 26 and the front surface of the n type base layer 13. More plainly, the gate electrode 18 is formed in a pattern having an opening in the central region of the p type base layer 15 in each unit cell 24 and the inner edge region of the n+ type source layer 16 continuous to the central region. In other words, the gate electrode 18 is formed to control a plurality of unit cells 24 in common.

[0053] The p type guard ring 11 may be a semiconductor layer doped with p type impurities, more specifically, a semiconductor layer formed by doping the n type base layer 13 with the p type impurities. As the p type impurities, the above-mentioned p type impurities may be used. The p type guard ring 11 may be a closed region surrounding the active region 3 when viewed from top (see FIG. 1). The p type guard ring 11 may be plural as shown in FIG. 2 or may be singular. The p type guard ring 11 extends toward the n.sup.+ type drain layer 12 up to a position deeper than the bottom of the p type base layer 15 in the n type base layer 13. More specifically, the p type guard ring 11 may have the same depth as the depth of the p type column layer 14.

[0054] The field insulating film 19 may be formed of, e.g., a silicon oxide film, a silicon astride film, a silicon oxynitride film, a hafnium oxide film, an alumina film or a tantalum oxide film. The field insulating film 19 is formed so as to cover at least a plurality of p type guard rings 11. The field insulating film 19 is thicker than the gate insulating film 17 and may have a thickness of, e.g., 1 μm to 7 μm.

[0055] The field embedded electrode 20 may be formed so as to face the p type guard ring 11 via the field insulating film 19. For example, the field embedded electrode 20 may be formed so as to selectively face at least one of a plurality of p type guard rings 11 (e.g., at least the innermost peripheral p type guard ring 11 and a p type guard ring 11 adjacent to the innermost peripheral p type guard ring 11 from outside) and not to face the remaining p type guard rings 11. The field embedded electrode 20 may be made of, e.g., polysilicon having resistance decreased by being doped with impurities. The field embedded electrode 20 may be formed in the same step as the gate electrode 18. The field embedded electrode 20 may be fixed to a source potential at a position (not shown).

[0056] The interlayer insulating film 21 may be formed of, e.g., an insulating material such as a silicon oxide film, a silicon nitride film, tetraethoxysilane (TEOS) or the like. The interlayer insulating film 21 covers an upper surface and side surfaces of the gate electrode 18 and an upper surface and side surfaces of the field embedded electrode 20 and is formed in a pattern having contact holes 27 in the central region of the p type base layer 15 in each unit cell 24 and the inner edge region of the n.sup.+ type source layer 16 continuous to the central region.

[0057] The source pad 8 is formed so as to cover the front surface of the interlayer insulating film 21 and to be embedded in the contact holes 27 of each unit cell 24. Thus, the source pad 8 is in ohmic contact with the n.sup.+ type source layer 16. Therefore, the source pad 8 is connected in parallel to the plurality of unit cells 24 and is configured such that the total current is flown into the plurality of unit cells 24. In addition, the source pad 8 is in ohmic contact with the p type base layer 15 of each unit cell 24 via the contact holes 27 and stabilizes the potential of the p type base layer 15.

[0058] The field plate 10 is formed on the front surface of the interlayer insulating film 21. The field plate 10 may face the field embedded electrode 20 via the interlayer insulating film 21. The drain electrode 22 is made of metal such as aluminum or the like. The drain electrode 22 is formed on the rear surface of the n.sup.+ type drain layer 12 (a surface in the opposite side to the n type base layer 13, or the lower surface in FIG. 2). Thus, the drain electrode 22 is connected in parallel to the plurality of unit cells 24 and is configured such that the total current is flown into the plurality of unit cells 24. A rear surface contact region 12a having a selective high n type impurity concentration may be formed in the vicinity of an interface with the drain electrode 22 of the n.sup.+ type drain layer 12.

[0059] With the drain electrode 22 set to a higher potential in comparison to a potential of the source pad 8, when a power supply is connected between the source pad 8 and the drain electrode 22, a reverse bias is applied to the parasitic diode 25. At this time, when a control voltage lower than a predetermined threshold voltage is applied to the gate electrode 18, no current path is formed between the drain and the source. In other words, the semiconductor device 1 is in a turn-off state. On the other hand, when a control voltage equal to or higher than the threshold voltage is applied to the gate electrode 18, electrons are attracted to the front surface of the channel region 26, thereby forming an inversion layer (channel). Thus, conduction is made between the n.sup.+ type source layer 16 and the n type base layer 13. In other words, a current path ranging from the source pad 8 to the drain electrode 22 through the n.sup.+ type source layer 16, the inversion layer of the channel region 26, the n type base layer 13 and the n.sup.+ type drain layer 12 in this order is formed.

[0060] When the semiconductor device 1 is applied to an inverter circuit for driving an inductive load such as an electric motor or the like, there is a case where the source pad 8 has a higher potential than the drain electrode 22 and a forward current flows in the parasitic diode 25. Thereafter, when the source pad 8 has a lower potential than the drain electrode 22, the parasitic diode 25 enters a reverse bias state. At this time, a depletion layer is spread from the pn junction of the parasitic diode 25, carriers (holes) injected into the n type base layer 13 are moved to the source pad 8, and carriers (electrons) injected into the p type base layer 15 and the p type column layer 14 are moved to the drain electrode 22. According to such movement of carriers, a reverse recovery current flows. This reverse recovery current once increases and thereafter decreases. Time taken until the magnitude of the reverse recovery current decreases to 10% of its maximum value after the forward current of the diode becomes 0 (zero) is called “reverse recovery time.”

[0061] The crystal defect region 23 contributes to a reduction of the reverse recovery time. The crystal defect region 23 is a region formed by irradiating charged particles, starting from the n.sup.+ type drain layer 12. A lot of recombination centers to be lost by trapping and recombining carriers exist in the crystal defect region 23. Therefore, since carriers can be quickly lost to shorten a carrier lifetime when the reverse recovery effect occurs, it is possible to reduce the reverse recovery time and the reverse recovery current.

[0062] The crystal defect region 23 is locally formed to be spread thinly (e.g., with a thickness of 10 μm to 15 μm) at a predetermined depth position from the rear surface of the n+ type drain layer 12 (an interface with the drain electrode 22) within the n type base layer 13. The thickness of the crystal defect region 23 in the depth direction is determined depending on, e.g., ion species, irradiation energy and so on. For example, a half thickness of the crystal defect region 23 is about 10 μm for .sup.3He.sup.++ (24 MeV). The crystal defect region 23 includes an active side crystal defect region 28 and an inactive side crystal defect region 29 which are at different depths (from the rear surface of the n.sup.+ type drain layer 12) within the n type base layer 13.

[0063] The active side crystal defect region 28 is located near the bottom 14a of the p type column layer 14. The active side crystal defect region 28 may be in contact with the bottom 14a of the p type column layer 14 or may be located between the bottom 14a of the p type column layer 14 while the n.sup.+ type drain layer 12 does not make contact with the p type column layer 14. In some embodiments, a distance from a half thickness position of the active side crystal defect region 28 in its thickness direction to the bottom 14a of the p type column layer 14 may be shorter than a distance from a middle position in the thickness direction between the bottom 14a of the p type column layer 14 and the front surface the n.sup.+ type drain layer 12 and the bottom 14a of the p type column layer 14. More specifically, the half thickness position of the active side crystal defect region 28 may be located within 5 μm from the bottom 14a of the p type column layer 14. The location of the active side crystal defect region 28 close to the bottom 14a of the p type column layer 14 is effective in reducing the reverse recovery time, whereas the location of the active side crystal defect region 28 distant from the bottom 14a of the p type column layer 14 is effective in reducing a drain-source leak current.

[0064] Thereafter, the inactive side crystal defect region 29, which has no direct contribution to the turn-on operation of the semiconductor device 1 and faces the p type guard ring 11, is located away from the bottom 11a of the p type guard ring 11. In some embodiments, a distance from a half thickness position of the inactive side crystal defect region 29 in its thickness direction to the n.sup.+ type drain layer 12 is shorter than a distance from a middle position in the thickness direction between the bottom 11a of the p type guard ring 11 and the surface of the n.sup.+ type drain layer 12 to the n.sup.+ type drain layer 12. More specifically, the half thickness position of the inactive side crystal defect region 29 may be formed to be separated from the bottom 11a of the p type guard ring 11 by 10 μm or more. Thus, in the inactive region 4, it is possible to suppress an effect caused by forming the crystal defect region 23 and reduce the drain-source leak current, thereby preventing a breakdown voltage of the semiconductor device 1 from decreasing. In addition, although not shown in FIG. 2, the inactive side crystal defect region 29 may be located below the gate pad region 5 of FIG. 1.

[0065] The crystal defect region 23 can be formed by irradiating protons or charged particles such as .sup.3He.sup.++, .sup.4He.sup.++ or the like. In particular, helium atom nuclei (.sup.3He.sup.++ or .sup.4He.sup.++), which is larger in mass, may be used since they can narrow a distribution range of a crystal defect generation layer in its thickness direction and can locally distribute the crystal defect generation layer in a narrow range in the thickness direction.

[0066] Next, a method of manufacturing the semiconductor device 1 will be described in detail. Although this embodiment employs a first method shown in FIGS. 3A to 3E and a second method shown in FIGS. 4A to 4E, the method of manufacturing the semiconductor device 1 is not limited thereto.

<First Method>

[0067] FIGS. 3A to 3E are views illustrating some sequential steps in a process of manufacturing the semiconductor device 1.

[0068] First, as illustrated in FIG. 3A, an MISFET structure is formed on a surficial layer portion of the semiconductor substrate 2. At this time, the p type column layer 14 and the p type guard ring 11 may be formed in the same ion implantation step. Next, the n.sup.+ type drain layer 12 (base substrate) of the semiconductor substrate 2 is thinned by grinding, starting from its rear surface side, as necessary. The grinding amount is not particularly limited but may be such an amount that the n.sup.+ type drain layer 12 has a thickness of 250 μm to 350 μm after being ground. When the thickness after being ground falls within this range, it is easy to secure an absorber thickness for precise control (e.g., control by 1 μm) of the range of charged particles.

[0069] Subsequently, as illustrated in FIG. 3B, a resist film 30 as one example of a mask of the present disclosure which covers the inactive region 4 and has an opening 31 on the active region 3 is formed on the rear surface of the semiconductor substrate 2. The opening 31 selectively exposes the active region 3, for example as indicated by a broken line hatching in FIG. 1. Therefore, the gate pad region 5 and the peripheral field region 6 are in a state of being covered by the resist film 30.

[0070] In addition, prior to the formation of the resist film 30, a protective film (not shown) may be formed on the front surface of the semiconductor substrate 2. By forming the protective film, the MISFET structure on the front surface can be protected from an etching step shown in FIG. 3C. For example, a resist film may be used as such a protective film. More specifically, when a positive resist film is entirely coated and developed on the front surface and the same film as the positive resist film is used as the resist film 30, the resist film may not be removed from the front surface when forming the opening 31.

[0071] Subsequently, as illustrated in FIG. 3C, the semiconductor substrate 2 is etched through the resist film 30. This etching is performed by deep etching and an aimed depth may range from, e.g., 10 μm to 100 μm. in some embodiments, the aimed depth may he sufficiently larger than a half thickness of the range of irradiated charged particles. Thus, a concave portion 32 is formed in the semiconductor substrate 2 (the n.sup.+ type drain layer 12). The depth of the concave portion 32 provides a level difference 33 between the active region 3 (the bottom of the concave portion 32) and the inactive region 4 (the rear surface other than the concave portion 32) in the rear surface of the semiconductor device 2. Thereafter, the resist film 30 and the protective film (not shown) on the front surface of the semiconductor substrate 2 are removed.

[0072] Subsequently, as illustrated in FIG. 3D, the irradiation of charged particles is performed, starting from the n.sup.+ type drain layer 12 side. Examples of the charged particles irradiated at this time may include protons, .sup.3He.sup.++ and .sup.4He.sup.++. The range (implantation depth) of the charged particles is determined, e.g., with a priority put on the position of the active side crystal defect region 28. An absorber for decreasing acceleration energy of the charged particle ions or energy of the charged particle ions is adjusted to allow the active side crystal defect region 28 to be formed in the vicinity of the bottom 14a of the p type column layer 14. For example, the irradiation energy of the charged particles (e.g., .sup.3H.sup.++) may be about 15 MeV to 30 MeV. For example, the typical helium ion energy by cyclotron is 10 MeV to 100 MeV. in addition, a dose of the charged particles (e.g., .sup.3H.sup.++) may be, e.g., about 1×10.sup.11/cm.sup.2 to 1×10.sup.13/cm.sup.2. Thus, the crystal defect region 23 is formed.

[0073] Subsequently, as illustrated in FIG. 3E, the n.sup.+ type drain layer 12 (base substrate) of the semiconductor substrate 2 is ground and flattened, starting from its rear surface. The grinding amount is not particularly limited as long as it can remove the level difference 33 and flatten the rear surface, but may be such an amount that the n.sup.+ type drain layer 12 has a thickness of 90 μm to 310 μm after being ground.

[0074] Subsequently, for example, heat treatment at a low temperature as one example of a first temperature of the present disclosure (low temperature annealing) is performed. Thus, the irradiated charged particles are donorized (activated). When .sup.3He.sup.++ is selected as the charged particles, the introduced .sup.3He.sup.++ can be donorized by heat treatment at, e.g., about 320 degrees C. to 380 degrees C. (e.g., 350 degrees C.) for, e.g., about 30 minutes to 90 minutes (e.g., 60 minutes).

[0075] In this embodiment, by irradiating a particle ray over the entire rear surface of the n.sup.+ type drain layer 12 in which the level difference 33 is formed, it is possible to form a level difference 39 between the active side crystal defect region 28 and the inactive side crystal defect region 29 in the active region 3 and the inactive region 4 with the particle ray of the same range. Therefore, it is possible to reliably separate an active area (the active side crystal defect region 28) to control the carrier lifetime from an inactive area (the inactive side crystal defect region 29).

[0076] This embodiment is characterized by using the level difference 33 formed in the semiconductor substrate by a semiconductor process to substantially separate a carrier lifetime control active area from a carrier lifetime control inactive area in a relatively simple way and with high precision of position alignment, without shielding the carrier lifetime control inactive area from the particle ray. If the carrier lifetime control inactive area is to be shielded by a mask, it is necessary to form a resist film, an insulating film and a metal film which will largely increase the thickness of the semiconductor substrate by, e.g., several tens of μm or more, which is impractical from the viewpoint of technical and productive efficiency. In addition, in a case where the particle ray is shielded by overlaying the semiconductor substrate with a metal plate which is cut to include an opening pattern, there is a problem of a remarkably poor precision of dimension or position alignment as compared to a semiconductor process keeping the precision at several μm or less. Meanwhile, in this embodiment, since the resist film 30 is patterned by photolithography in order to separate the carrier lifetime control active area (the active side crystal defect region 28) from the carrier lifetime control inactive area (the inactive side crystal defect region 29), the areas can be designated with the precision of several μm or less. In addition, since an existing semiconductor device manufacturing apparatus may be used, such method is especially reasonable and useful in respect of productivity.

[0077] Thereafter, implantation of n type impurities (e.g., As) is performed, starting from the n.sup.+ type drain layer 12, and, subsequently, heat treatment is performed at a low temperature as one example of a second temperature of the present disclosure which is lower than the activation temperature (e.g., 320 degrees C. to 350 degrees C.) of the charged particles. One example of such heat treatment may include a method of laser annealing. Thus, the implanted n type impurities are donorized (activated) to form the rear surface contact region 12a (not shown). By making the heat treatment temperature at this time lower than the activation temperature of the charged particles, the charged particles can further be activated when forming the rear surface contact region 12a, thereby preventing the degree of diffusion of the crystal defect region 23 from fluctuating. The drain electrode 22 is formed after forming the rear surface contact region 12a. The semiconductor device 1 can be obtained through the above-described process.

<Second Method>

[0078] FIGS. 4A to 4E are views illustrating some sequential steps in a process of manufacturing the semiconductor device 1.

[0079] First, as illustrated in FIG. 4A, the same step as FIG. 3A is performed. In other words, an MISFET structure is formed on a surficial layer portion of the semiconductor substrate 2. Subsequently, the n.sup.+ type drain layer 12 (base substrate) of the semiconductor substrate 2 is thinned by grinding, starting from its rear surface side, as necessary. The grinding amount may be the same as one described above.

[0080] Subsequently, as illustrated in FIG. 4B, an insulating film 34 as one example of a first mask of the present disclosure is formed on the entire rear surface of the n.sup.+ type drain layer 12, for example by a CVD method. The insulating film 34 may be formed of, e.g., a silicon oxide film, a silicon nitride film or the like. The thickness of the insulating film 34 may be, e.g., 5 μm to 10 μm.

[0081] Subsequently, as illustrated in FIG. 4C, a resist film 35 as one example of a second mask of the present disclosure which covers the inactive region 4 and has an opening 36 on the active region 3 is formed on the insulating film 34. The opening 36 selectively exposes the active region 3, for example as indicated by a broken line hatching in FIG. 1. Therefore, the insulating film 34 on the gate pad region 5 and the peripheral field region 6 is in a state of being covered with the resist film 35. Further, in this case, in the same manner as described above, prior to forming the resist film 35, a protective film (not shown) may be formed on the front surface of the semiconductor substrate 2.

[0082] Subsequently, the insulating film 34 is etched through the resist film 35. This etching is performed up to the rear surface of the semiconductor substrate 2 (the n.sup.+ type drain layer 12). Thus, an opening 37 is formed in the insulating film 34. This opening 37 provides a level difference 38 between the active region 3 (the bottom of the opening 37, that is, the rear surface of the n.sup.+ type drain layer 12) and the inactive region 4 (the rear surface of the insulating film 34) in the rear surface of the semiconductor device 2. The level difference 38 is equal to the thickness of the insulating film 34. Thereafter, the resist film 35 and the protective film (not shown) on the front surface of the semiconductor substrate 2 are removed.

[0083] Subsequently, as illustrated in FIG. 4D, the irradiation of charged particles is performed, starting from the n.sup.+ type drain layer 12 side. Examples of the charged particles irradiated at this time may include protons, .sup.3He.sup.++ and .sup.4He.sup.++. The range (implantation depth) of the charged particles is determined, e.g., with a priority put on the position of the active side crystal defect region 28. An absorber for decreasing acceleration energy of the charged particle ions or energy of the charged particle ions is adjusted to allow the active side crystal defect region 28 to be formed in the vicinity of the bottom 14a of the p type column layer 14. For example, the irradiation energy of the charged particles (e.g., .sup.3H.sup.++) may be about 15 MeV to 30 MeV. In addition, a dose of the charged particles (e.g., .sup.3H.sup.++) may be, e.g., about 1×10.sup.11/cm.sup.2 to 1×10.sup.13/cm.sup.2. Thus, the crystal defect region 23 is formed.

[0084] Subsequently, as illustrated in FIG. 4E, the n.sup.+ type drain layer 12 (base substrate) of the semiconductor substrate 2 is ground and flattened, starting from its rear surface. The grinding amount is not particularly limited but may be such an amount that the n.sup.+ type drain layer 12 has a thickness of 90 μm to 310 μm after being ground.

[0085] Subsequently, in the same manner as described above, heat treatment is performed at a low temperature as one example of a first temperature of the present disclosure (low temperature annealing). Thus, the irradiated charged particles are donorized (activated).

[0086] In this embodiment, by irradiating a particle ray over the entire rear surface of the n.sup.+ type drain layer 12 in which the level difference 38 is formed, it is possible to form a level difference 40 between the active side crystal defect region 28 and the inactive side crystal defect region 29 in the active region 3 and the inactive region 4 with the particle ray of the same range. This level difference 40 makes it possible to form the active side crystal defect region 28 and the inactive side crystal defect region 29 at different depths within the n type base layer 13 in the active region 3 and the inactive region 4, respectively. Moreover, when forming the level difference 38, since the etching of the insulating film 34 can be stopped at the rear surface of the n.sup.+ type drain layer 12, it is possible to reduce a variation in depth at the bottom of the level difference 38. This can make a start point of implantation of the charged particles in the active region 3 substantially constant, which can result in reduction of a variation in depth position of the active side crystal defect region 28.

[0087] In addition, this embodiment eliminates a need to completely shield the implantation of the charged particles into the inactive region 4 since it is not the case that only the active region 3 is selectively irradiated with the charged particles. Therefore, in the same manner as described above, it is possible to eliminate the unreasonableness and usefulness in respect of productivity.

[0088] Thereafter, in the same manner as described above, the implantation of n type impurities (e.g., As) is performed, starting from the n.sup.+ type drain layer 12 side, and, subsequently, heat treatment is performed at a low temperature as one example of a second temperature of the present disclosure which is lower than the activation temperature (e.g., 320 degrees C. to 350 degrees C.) of the charged particles. Thus, the implanted n type impurities are donorized (activated) to form the rear surface contact region 12a (not shown). The drain electrode 22 is formed after forming the rear surface contact region 12a. The semiconductor device 1 can be obtained through the above-described process.

[0089] While one embodiment of the present disclosure has been described in the above, the present disclosure may be practiced in different forms. For example, an alpha ray, heavy metal or the like may be used as particles for forming the crystal defect region 23. In addition, an element structure formed on the semiconductor substrate 2 is not limited to a vertical MISFET structure but may be, e.g., a vertical IGBT, a pn diode or the like. For the vertical IGBT, in the same manner as described above, the active side crystal defect region 28 may be formed in the vicinity of a parasitic diode. For the pn diode, the active side crystal defect region 28 may be formed in the vicinity of a pn junction of the pn diode.

[0090] Further, various modifications and changes in design are possible without departing from the scope defined in the claims.

EXAMPLES

[0091] Next, verification on the following points was made in order to demonstrate the operation and effects of the present disclosure.

(1) Variation of Peak Breakdown Voltage with Respect to Ion Stop Position

[0092] This is to verify that the breakdown voltage of the semiconductor device 1 can be prevented from being decreased when a position of the crystal defect region 23 is separated from the pn junction.

[0093] Specifically, in the structure shown in FIG. 2, assuming that an estimated distance from the bottom 14a of the p type column layer 14 to the rear surface of the n.sup.+ type drain layer 12 is 175 μm, charged particles (ions) were irradiated in such a manner that the charged particles were stopped at positions of 150 μm, 155 μm, 160 μm and 165 μm from the rear surface of the n.sup.+ type drain layer 12. In each experiment, measurement of BVDSS was made for six semiconductor wafers S1 to S6. Variations of peak breakdown voltage before and after irradiation in each experiment are shown in FIGS. 5 to 8. In each of FIGS. 5 to 8, a horizontal axis represents a pn charge balance of a super junction MISFET structure. A peak breakdown voltage at a balance of substantially p=n is shown near 0 (zero) of the horizontal axis. In each of FIGS. 5 to 8, a vertical axis represents a breakdown voltage BVDSS. In each of FIGS. 5 to 8, numerals in the left side indicate “(distance from the rear surface of the n.sup.+ type drain layer 12/estimated distance from the pn junction of the bottom 14a of the p type column layer 14) of the ion stop position.”

[0094] It can be seen from FIGS. 5 to 8 that the peak breakdown voltage of the semiconductor device 1 is greatly varied when the estimated distance from the pn junction of the bottom 14a of the p type column layer 14 is 5 μm, whereas the variation is decreased with the increase in the estimated distance, showing little or no variation at 15 μm (FIGS. 6) and 20 μm (FIG. 5). Therefore, it is found from this result that, when the crystal defect region 23 (the inactive side crystal defect region 29) is formed at a position distant from the p type guard ring 11 having the breakdown voltage structure as described above, it is possible to reduce an effect by the inactive side crystal defect region 29 and maintain the function of the breakdown voltage structure of the semiconductor device 1.

(2) Effect by Masking of Peripheral Field region

[0095] This is to verify that the breakdown voltage of the semiconductor device 1 can be prevented from being decreased when the crystal defect region 23 is formed in the inactive region 4.

[0096] Specifically, a TEG (Test Element Group) of pattern 1 and pattern 2 shown in FIG. 9 was fabricated into a silicon wafer in which a number of MISFET structures of FIG. 2 were built. The pattern 1 is a pattern in which the rear surface of the semiconductor device 1 is not covered by a mask and charged particles are implanted into the entire rear surface. The pattern 2 is a pattern in which the inactive region 4 of the semiconductor device 1 is covered by a mask plate and charged particles are not implanted into the inactive region 4. For each of the patterns 1 and 2, assuming that an estimated distance from the bottom 14a of the p type column layer 14 to the rear surface of the n.sup.+ type drain layer 12 is 175 μm, charged particles were irradiated in such a manner that the charged particles were stopped at positions of 165 μm and 175 μm from the rear surface of the n.sup.+ type drain layer 12. The irradiation of charged particles was performed under the conditions of ion species : .sup.3He.sup.++, dose : 1.0×10.sup.12/cm.sup.2 and low temperature annealing : 350 degrees C. for 60 minutes. Variations of peak breakdown voltage before and after irradiation in each experiment are shown in FIGS. 10 to 13. In each of FIGS. 10 to 13, a horizontal axis represents a pn charge balance of a super junction MISFET structure. A peak breakdown voltage at a balance of substantially p=n is shown near 0 (zero) of the horizontal axis. In each of FIGS. 10 to 13, a vertical axis represents a breakdown voltage BVDSS.

[0097] It can be seen from FIGS. 10 to 13 that, as a result that the crystal defect region 23 is formed in the vicinity of the bottom 14a of the p type column layer 14 of the active region 3, the pattern 2 (particularly FIG. 13) shows a slight variation of the peak breakdown voltage, which is about ½ of that of the pattern 1 (FIG. 12) under the same irradiation conditions. In other words, when the crystal defect region 23 is formed in the vicinity of the bottom 11a of the peripheral p type guard ring 11 as in the pattern 1, the breakdown voltage of the semiconductor device 1 is significantly decreased. Therefore, it is found from this result that, even when the crystal defect region 23 (the active side crystal defect region 28) is formed in the vicinity of the bottom 14a of the p type column layer 14 as described above, there is a low possibility that the breakdown voltage is decreased, but rather, the active side crystal defect region 28 preferentially works to reduce a reverse recovery time by trapping carriers (electrons). In addition, it is found that, when the crystal defect region 23 (the inactive side crystal defect region 29) is formed at a position distant from the p type guard ring 11 having the breakdown voltage structure as described above, it is possible to reduce an effect by the inactive side crystal defect region 29 and maintain the function of the breakdown voltage structure of the semiconductor device 1.

[0098] While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the novel methods and apparatuses described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures.