A semiconductor device may include at least one double-barrier resonant tunneling diode (DBRTD). The at least one DBRTD may include a first doped semiconductor layer and a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one DBRTD may further include an intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the intrinsic semiconductor layer, and a second doped semiconductor layer on the second superlattice layer.

A method includes doping a substrate with a dopant to form a first well region of a first core circuit and a second well region of a second core circuit; forming first and second semiconductor fins respectively over the first and second well regions and extending along a direction; forming a first gate stack across the first semiconductor fin and a second gate stack across the second semiconductor fin; forming a first source/drain adjoining the first semiconductor fin and a second source/drain adjoining the second semiconductor fin; and forming a first contact over the first source/drain and having a first width measured along the direction and a second contact over the second source/drain and having a second width measured along the direction, wherein the second width of the second contact is greater than the first width of the first contact.

Disclosed are structures and methods related to metallization of a gallium arsenide (GaAs) layer. In some embodiments, a tantalum nitride (TaN) layer can be formed on a doped GaAs layer, and a metal layer can be formed on the TaN layer. Such a structure can be included in a Schottky diode. In some embodiments, such a Schottky diode can be fabricated utilizing heterojunction bipolar transistor (HBT) processes.

Provided is an epitaxial substrate for semiconductor elements which suppresses an occurrence of current collapse. The epitaxial substrate for the semiconductor elements includes: a semi-insulating free-standing substrate formed of GaN being doped with Zn; a buffer layer being adjacent to the free-standing substrate; a channel layer being adjacent to the buffer layer; and a barrier layer being provided on an opposite side of the buffer layer with the channel layer therebetween, wherein the buffer layer is a diffusion suppressing layer formed of Al-doped GaN and suppresses diffusion of Zn from the free-standing substrate into the channel layer.

An epitaxial substrate for semiconductor elements which suppresses the occurrence of current collapse. The epitaxial substrate for the semiconductor elements includes: a semi-insulating free-standing substrate formed of GaN doped with Zn; a buffer layer adjacent to the free-standing substrate; a channel layer adjacent to the buffer layer; and a barrier layer provided on an opposite side of the buffer layer with the channel layer provided therebetween, wherein the buffer layer is a diffusion suppressing layer that suppresses the diffusion of Zn from the free-standing substrate into the channel layer.

A field effect transistor, a memory element, and a manufacturing method of a charge storage structure are provided. The memory element includes a plurality of field effect transistors, and each of the field effect transistors includes a substrate, a source region, a drain region, a gate conductive layer, and a charge storage structure. Both the source region and the drain region are located in the substrate and connected to an upper surface of the substrate. The source and drain regions are spaced apart from each other to define a channel region therebetween. The gate conductive layer is disposed over the upper surface and overlaps with the channel region. The charge storage structure disposed between the gate conductive layer and the channel region includes a ferroelectric material and a paraelectric material so that the charge storage structure has better capability of trapping charges and a higher switching speed.

Provided is a semiconductor-manufacturing apparatus that forms a plated film having a highly homogeneous thickness on a target surface of a semiconductor wafer through electroless plating. A semiconductor-manufacturing apparatus forms plated films on target surfaces of a plurality of wafers held by a carrier capable of holding the wafers. The semiconductor-manufacturing apparatus includes the following: a rectification mechanism including a rectification plate having a plurality of through-holes, the rectification mechanism being held by the carrier in such a manner that the rectification plate faces the target surface of each wafer; a bath in which a chemical solution for forming each plated film is stored, and in which the carrier, holding the plurality of wafers and the rectification mechanism, is immersed in the chemical solution; and a driver configured to shake the carrier as immersed in the bath with a relative positional relationship between each wafer and the through-holes kept constant.

The invention provides transient devices, including active and passive devices that electrically and/or physically transform upon application of at least one internal and/or external stimulus. Materials, modeling tools, manufacturing approaches, device designs and system level examples of transient electronics are provided.

In embodiments, a semiconductor gas sensor includes a substrate having a cavity, a first insulation layer formed on the substrate, including an exposure hole formed at a position corresponding to the cavity and a peripheral portion of the cavity, a second insulation layer formed on the first insulation layer, covering the exposure hole, a heating electrode formed on the second insulation layer, being formed at a position corresponding to the cavity, a sensing electrode formed over the heating electrode, being electrically insulated from the heating electrode and a detection layer covering the sensing electrode, being capable of having a variable resistance when acting with a predetermined kind of gas.

A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.