Disclosed is an ESD protection device, comprising: a semiconductor substrate; a semiconductor buried layer located in the semiconductor substrate; an epitaxial semiconductor layer located on the semiconductor substrate and comprising a first doped region and a second doped region, wherein the semiconductor substrate and the first doped region are of a first doping type, the semiconductor buried layer, the epitaxial semiconductor layer and the second doped region are of a second doping type, the first doping type and the second doping type are opposite to each other, and the first doped region forms a plurality of interfaces with the epitaxial semiconductor layer. The disclosure improves protection performance and maximum current bearing capacity without increasing parasitic capacitance of the ESD protection device.

In a physical quantity sensor, a contact part that is directly and electrically connected to an external circuit is formed in a support substrate, and the support substrate is maintained at a predetermined potential through the contact part. With this configuration, the support substrate is maintained at the predetermined potential without disposing an electrode in the interior of the semiconductor layer. For that reason, a processing precision can be restrained from being reduced in forming the movable electrode, and hence a detection precision can be restrained from being reduced.

A semiconductor device includes at least one first fin, a first contact plug, a first via, at least one second fin, at least one contact plug, and a second via. The first fin extends along a direction. The first contact plug overlaps the first fin and has a first width measured along the direction. The first via overlaps the first contact plug and has a first top surface. The second fin extends along the direction. The second contact plug overlaps the second fin and has a second width measured along the direction, in which the second width is greater than the first width. The second via overlaps the second contact plug and has a second top surface, in which an area the second top surface is greater than an area of the first top surface.

A method of forming a nanostructure comprises forming a directed self-assembly of nucleic acid structures on a patterned substrate. The patterned substrate comprises multiple regions. Each of the regions on the patterned substrate is specifically tailored for adsorption of specific nucleic acid structure in the directed self-assembly.

A method may include thinning a silicon wafer to a particular thickness. The particular thickness may be based on a passband frequency spectrum of an adjustable optical filter. The method may also include covering a surface of the silicon wafer with an optical coating. The optical coating may filter an optical signal and may be based on the passband frequency spectrum. The method may additionally include depositing a plurality of thermal tuning components on the coated silicon wafer. The plurality of thermal tuning components may adjust a passband frequency range of the adjustable optical filter by adjusting a temperature of the coated silicon wafer. The passband frequency range may be within the passband frequency spectrum. The method may include dividing the coated silicon wafer into a plurality of silicon wafer dies. Each silicon wafer die may include multiple thermal tuning components and may be the adjustable optical filter.

The invention provides a method of fabricating an electromechanical structure presenting a first substrate including a layer of monocrystalline material covered in a sacrificial layer that presents a free surface, the structure presenting a mechanical reinforcing pillar in the sacrificial layer, the method including etching a well region in the sacrificial layer to define a mechanical pillar; depositing a first functionalization layer of the first material to at least partially fill the well region and cover the free surface of the sacrificial layer around the well region; depositing a second material different from the first material for terminating the filling of the well region to thereby cover the first functionalization layer around the well region, planarizing the filler layer, the pillar being formed by the superposition of the first material and second material in the well region; and releasing the electromechanical structure by removing at least partially the sacrificial layer.

Disclosed is an ESD protection device, comprising: a semiconductor substrate; a semiconductor buried layer located in the semiconductor substrate; an epitaxial semiconductor layer located on the semiconductor substrate and comprising a first doped region and a second doped region, wherein the semiconductor substrate and the first doped region are of a first doping type, the semiconductor buried layer, the epitaxial semiconductor layer and the second doped region are of a second doping type, the first doping type and the second doping type are opposite to each other, and the first doped region forms a plurality of interfaces with the epitaxial semiconductor layer. The disclosure improves protection performance and maximum current bearing capacity without increasing parasitic capacitance of the ESD protection device.

A method for making a semiconductor device may include forming at least one double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, and forming a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming an intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the intrinsic semiconductor layer, and forming a second doped semiconductor layer on the second superlattice layer.

A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

Provided is an epitaxial substrate for semiconductor elements which suppresses an occurrence of current collapse. The epitaxial substrate for the semiconductor elements includes: a semi-insulating free-standing substrate formed of GaN being doped with Zn; a buffer layer being adjacent to the free-standing substrate; a channel layer being adjacent to the buffer layer; and a barrier layer being provided on an opposite side of the buffer layer with the channel layer therebetween, wherein the buffer layer is a diffusion suppressing layer that suppresses diffusion of Zn from the free-standing substrate into the channel layer.