Disclosed are structures and methods related to metallization of a gallium arsenide (GaAs) layer. In some embodiments, a tantalum nitride (TaN) layer can be formed on a doped GaAs layer, and a metal layer can be formed on the TaN layer. Such a structure can be included in a Schottky diode. In some embodiments, such a Schottky diode can be fabricated utilizing heterojunction bipolar transistor (HBT) processes.

The present application provides a logic gate device. The logic gate device includes a gate electrode, a gate insulating layer, a bottom electrode, a two-dimensional semiconductor layer, a first top electrode and a second electrode. The gate insulating layer is located on the gate electrode. The bottom electrode is located on the gate insulating layer. The two-dimensional semiconductor layer is located on the bottom electrode and simultaneously covers the gate insulating layer. The first top electrode and the second electrode are located on the two-dimensional semiconductor layer. The bottom electrode, the two-dimensional semiconductor layer and the gate insulating layer form an air gap, and the air gap is distributed at both sides of the bottom electrode. The gate electrode is configured to connect a gate voltage, and the first top electrode and the second top electrode are configured to connect a signal input terminal.

A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.

Disclosed are structures and methods related to metallization of a gallium arsenide (GaAs) layer. In some embodiments, a tantalum nitride (TaN) layer can be formed on a doped GaAs layer, and a metal layer can be formed on the TaN layer. Such a structure can be included in a Schottky diode. In some embodiments, such a Schottky diode can be fabricated utilizing heterojunction bipolar transistor (HBT) processes.

Disclosed are structures and methods related to metallization of a gallium arsenide (GaAs) layer. In some embodiments, a tantalum nitride (TaN) layer can be formed on a doped GaAs layer, and a metal layer can be formed on the TaN layer. Such a structure can be included in a Schottky diode. In some embodiments, such a Schottky diode can be fabricated utilizing heterojunction bipolar transistor (HBT) processes.

The invention relates to heterostructures including a layer of a two-dimensional material placed on a multiferroic layer. An ordered array of differing polarization domains and surface charges in the multiferroic layer produces corresponding domains having differing properties in the two-dimensional material. When the multiferroic layer is ferroelectric, the ferroelectric polarization domains in the layer produce local electric fields that penetrate the two-dimensional material. The local electric fields and surface charges can control the structural phase of the two-dimensional material, which in turn determines whether the two-dimensional material layer is insulating or metallic, has a band gap or no band gap, and whether it is magnetic or non-magnetic. Methods for producing the heterostructures are provided. Devices incorporating the heterostructures are also provided.

A multilayer stacking wafer bonding structure is provided in the present invention, including a logic wafer with a substrate and a logic circuit layer on the substrate, multiple memory wafers bonded sequentially on the logic circuit layer to form a first multilayer stacking structure, wherein each memory wafer includes a memory layer, a silicon layer on the memory layer and multiple oxide layers in trenches of the silicon layer, and the oxide layers in the memory wafers are aligned each other in a direction vertical to the substrate, and multiple through-oxide vias (TOV) extending through the memory layers and the oxide layers in the first multilayer stacking structure into the logic circuit layer, and the TOVs do not extend through any of the silicon layers.

A semiconductor device includes a gate structure including insulating layers and conductive layers that are alternately stacked, a channel layer located in the gate structure, a silicide layer located in the channel layer, and a memory layer surrounding the channel layer. At least one of the channel layer, the silicide layer, and the memory layer includes a halogen element.

A MOSFET used in a power conversion circuit including a reactor, a power source, the MOSFET, and a rectifier element, includes a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure, the n-type column region and the p-type column region are formed such that a total amount of a dopant in the p-type column region is set higher than a total amount of a dopant in the n-type column region, and the MOSFET is configured to be operated in response to turning on of the MOSFET such that at a center of the n-type column region as viewed in a plan view, a low electric field region having lower field intensity than areas of the n-type column region other than the center of the n-type column region appears.

Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having a controllable resistance. An example method for forming a semiconductor device includes forming a source terminal and a drain terminal of a field effect transistor (FET) on a substrate. The source terminal and the drain terminal are formed on either sides of a channel region. An energy barrier is formed adjacent to the source terminal and the channel region. A conductive gate is formed over the channel region.