A semiconductor device has a semiconductor package including a substrate with a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A metal mask having a fiducial marker is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The metal mask is removed after forming the shielding layer.

Structures that include an identification marking and fabrication methods for such structures. A chip is formed within a usable area of a wafer, and a marking region is formed on the wafer. The marking region is comprised of a conductor used to form a last metal layer of an interconnect structure for the chip. The identification marking is formed in the conductor of the marking region. After the identification marking is formed, a dielectric layer is deposited on the marking region. The dielectric layer on the marking region is planarized.

The present disclosure provides improved approaches for marking and individual tracking of solar cells. These approaches can be used to identify key manufacturing process steps requiring optimization and/or significant factors extending solar cell lifetime. The approaches described herein for marking and individual tracking of solar cells avoid or greatly minimize any negative impact on solar cell performance while improving quality control of solar cells across multiple manufacturing steps and throughout the entire solar cell lifecycle. Embodiments described herein include a solar cell comprising a substrate having a front side and a back side. The substrate comprises at least one diffusion region of a first polarity. A first set of conductive conduits in the first set is electrically coupled to at least one active diffusion region of a first polarity. The solar cell further comprises a marking above an inactive region of the substrate. The marking can provide information about a particular cell which can be read or scanned during cell manufacturing and/or in the field during the operational life of the cell.

A substrate includes a ceramic layer, a metal layer fixed in a planar manner on a surface side of the ceramic layer and a cutout arranged in an edge region of the metal layer. The cutout in the edge region codes information. A multiple substrate having a plurality of these substrates is also provided, as is a method for producing the substrate.

A semiconductor package is provided. The semiconductor package may include a substrate, a chip stack disposed on the substrate, the chip stack including a plurality of semiconductor chips, a plurality of bonding wires electrically connecting the substrate to the plurality of semiconductor chips, a reinforcement layer disposed on the chip stack, and a molding layer surrounding side surfaces of the chip stack and the bonding wires and contacting side surfaces of the reinforcement layer. The reinforcement layer may include a lower layer including an adhesive, an intermediate layer disposed on the lower layer, and an upper layer disposed on the intermediate layer. The intermediate layer may have elongation in a range of 5% to 70%. The upper layer may have elongation less than 5%.

Techniques and mechanisms for providing physically unclonable function (PUF) circuitry at a substrate which supports coupling to an integrated circuit (IC) chip. In an embodiment, the substrate comprises an array of electrodes which extend in a level of metallization at a side of the insulator layer. A cap layer, disposed on the array, is in contact with the electrodes and with a portion of the insulator layer which is between the electrodes. A material of the cap layer has a different composition or microstructure than the metallization. Regions of the cap layer variously provide respective impedances each between a corresponding two electrodes. In other embodiments, the substrate includes (or couples to) integrated circuitry that is operable to determine security information based on the detection of one or more such impedances.

A semiconductor device has a semiconductor package including a substrate with a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A metal mask having a fiducial marker is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The metal mask is removed after forming the shielding layer.

A semiconductor element separated from an original substrate includes: an element substrate; and an element constitution part formed on the element substrate, wherein a pattern indicating a position of the semiconductor element before separating the semiconductor element from the original substrate is formed on at least one of the element substrate and the element constitution part.

An electronic semiconductor component with a housing structure and a cavity introduced into the housing structure is specified. The cavity comprises a base surface. Furthermore, the electronic semiconductor component comprises an auxiliary layer arranged on the base surface of the cavity and a marking penetrating the auxiliary layer at least as far as the base surface of the cavity. The marking comprises an optical contrast that depends on both an optical property of the housing structure and an optical property of the auxiliary layer. Furthermore, a method for producing an electronic semiconductor component is given.

An optoelectronic component includes at least one optoelectronic semiconductor chip and an electronic first storage medium. The first storage medium electrically stores first component information. The component can be uniquely identified via the first component information. The optoelectronic component also includes a second storage medium which can be read out wirelessly at least in an unmounted state of the component. The second storage medium stores second component information that is representative of the first component information.