A method for manufacturing a semiconductor device includes forming semiconductor devices from a semiconductor wafer and identifying a position of the semiconductor device in the semiconductor wafer, wherein the forming the semiconductor devices includes forming a first repeating pattern including i semiconductor devices each having a unique pattern, forming a second repeating pattern including j semiconductor devices each having a unique pattern, defining semiconductor devices on the semiconductor wafer such that each of the k semiconductor devices has a unique pattern based on the first and second repeating patterns, and grinding a backside of the semiconductor wafer, wherein each unique pattern of the k semiconductor devices is composed of a combination of the unique patterns of the first and second repeating patterns, wherein the position of the semiconductor device is identified based on the unique patterns of the first and second repeating patterns and an angle of a grinding mark.

A technique for marking semiconductor devices with an identifiable mark or alphanumeric text yields a high-contrast, easily distinguishable mark on an electrical terminal of the device without impacting the device's breakdown voltage capability and without compromising the solderability and wire bondability of the terminal. This approach deposits the mark on the terminal as a patterned layer of palladium, which offers good contrast with the base metal of the terminal and maintains the solderability and bondability of the terminal.

A semiconductor device with an identification structure is provided. The semiconductor device includes a substrate and a metallization structure over the substrate. The metallization structure includes an interconnection region having a plurality of metal layers and an identification region isolated from the interconnection region. The identification region has an identification structure leveled with one of the metal layer. The identification structure includes at least one exposing recess and at least one exposing fuse. A method for manufacturing a semiconductor device with an identification structure and a method for tracing a production information of a semiconductor device are also provided.

A silicon wafer forming method includes: a block ingot forming step of cutting a silicon ingot to form block ingots; a planarizing step of grinding an end face of the block ingot to planarize the end face; a separation layer forming step of applying a laser beam of such a wavelength as to be transmitted through silicon to the block ingot, with a focal point of the laser beam positioned in the inside of the block ingot at a depth from the end face of the block ingot corresponding to the thickness of the wafer to be formed, to form a separation layer; and a wafer forming step of separating the silicon wafer to be formed from the separation layer.

A method of producing a silicon wafer includes: a laser mark printing step of printing a laser mark having a plurality of dots on a silicon wafer; an etching step of performing etching on at least a laser-mark printed region in a surface of the silicon wafer; and a polishing step of performing polishing on both surfaces of the silicon wafer having been subjected to the etching step. In the laser mark printing step, each of the plurality of dots is formed by a first step of irradiating a predetermined position on a periphery of the silicon wafer with laser light of a first beam diameter thereby forming a first portion of the dot and a second step of irradiating the predetermined position with laser light of a second beam diameter that is smaller than the first beam diameter thereby forming a second portion of the dot.

Provided is a chemical-mechanical polishing composition comprising an abrasive, a basic component, at least one compound selected from the group consisting of a quaternary polyammonium salt, a quaternary ammonium salt having 6 or more carbon atoms, and an alkylated polymer having an amide structure, and an aqueous carrier; a rinse composition comprising the at least one compound and an aqueous carrier, as well as a method of chemically-mechanically polishing a substrate, and a method of rinsing a substrate, in which the respective compositions are used.

The disclosure provides an integrated circuit (IC) structure with fluorescent materials, and related methods. An IC structure according to the disclosure may include a layer of fluorescent material on an IC component. The layer of fluorescent material defines a portion of an identification marker for the IC structure.

The present invention provides a shield package having a highly distinctive pattern formed on a surface of a shield layer. The shield package of the present invention includes a package in which an electronic component is sealed with a resin layer, and a shield layer covering the package, wherein a surface of the resin layer includes a drawing area drawn with lines and/or dots by aggregation of multiple grooves, and a non-drawing area other than the drawing area, multiple depressions originating from the grooves are formed on a surface of the shield layer on the drawing area, and the depressions are aggregated to draw a pattern with lines and/or dots.

A chip package unit includes: a base material; at least one chip, disposed on the base material; a package material, enclosing the base material and the chip; and at least one heat dissipation paste curing layer, formed by curing the heat dissipation paste, on a top side of the package material or a back side of the chip in a printed pattern.

A semiconductor device wafer includes a plurality of device patterns formed in or over a semiconductor substrate, and a scribe area from which the device patterns are excluded. A plurality of dummy features are located in at least one material level in the scribe area, including over laser scribe dots formed in the semiconductor substrate.