A method of forming a charge pattern on a microchip includes depositing a material on the surface of the microchip, and immersing the microchip in a fluid to develop charge in or on the material through interaction with the surrounding fluid.

A chip on film package structure including a flexible film, a patterned metal layer, a chip, a patterned solder resist layer, and a code-included pattern is provided. The flexible film comprises a chip mounting region and a peripheral region surrounding the chip mounting region. The patterned metal layer disposed on the flexible film. The chip mounted on the chip mounting region and electrically connected to the patterned metal layer. The patterned solder resist layer exposing the chip mounting region and covering a part of the patterned metal layer. The code-included pattern disposed on the peripheral region of the flexible film. The code-included pattern comprises a plurality of machine-readable data. A method for reading a code-included pattern on a package structure is also provided.

A method for transferring a plurality of die operatively associated with a transfer apparatus to a glass substrate to form a circuit component. The transfer occurs by positioning the glass substrate to face a first surface of a die carrier carrying multiple die. A reciprocating transfer member thrusts against a second surface of the die carrier to actuate the transfer member thereby causing a localized deflection of the die carrier in a direction of the surface of the glass substrate to position an initial die proximate to the glass substrate. The initial die transfers directly to a circuit trace on the glass substrate. At least one of the die carrier or the transfer member is then shifted such that the transfer member aligns with a subsequent die on the first surface of the die carrier. The acts of actuating, transferring, and shifting are repeated to effectuate a transfer of the multiple die onto the glass substrate.

The present invention includes a chip, a plastic film layer, and an electroplated layer. A front side and a back side of the chip each comprises a signal contact. The plastic film layer covers the chip and includes a first via and a second via. The first via is formed adjacent to the chip, and the second via is formed extending to the signal contact of the front side. A conductive layer is added in the first and the second via. The conductive layer in the second via is electrically connected to the signal contact of the front side. Through the electroplated layer, the signal contact on the back side is electrically connected to the conductive layer in the first via. The conductive layer protrudes from the plastic film layer as conductive terminals. The present invention achieves electrical connection of the chip without using expensive die bonding materials.

Provided are package-on-package (POP)-type semiconductor packages including a lower package having a first size and including a lower package substrate in which a lower semiconductor chip is, an upper redistribution structure on the lower package substrate and the lower semiconductor chip, and alignment marks. The packages may also include an upper package having a second size smaller than the first size and including an upper package substrate and an upper semiconductor chip. The upper package substrate may be mounted on the upper redistribution structure of the lower package and electrically connected to the lower package, and the upper semiconductor chip may be on the upper package substrate. The alignment marks may be used for identifying the upper package, and the alignment marks may be below and near outer boundaries of the upper package on the lower package.

In one example, a method of manufacturing a semiconductor device includes providing a substrate having substrate terminals and providing a component having a first component terminal and a second component terminal adjacent to a first major side of the component. The method includes providing a clip structure having a first clip, a second clip, and a clip connector coupling the first clip to the second clip. The method includes coupling the first clip to the first component terminal and a first substrate terminal and coupling the second clip to a second substrate terminal. The method includes encapsulating the component, portions of the substrate, and portions of the clip structure. the method includes removing a sacrificial portion of the clip connector while leaving a first portion of the clip connector attached to the first clip and leaving a second portion of the clip connector attached to the second clip. In some examples, the first portion of the clip connector includes a first portion surface, the second portion of the clip connector includes a second portion surface, and the first portion surface and the second portion surface are exposed from a top side of the encapsulant after the removing. Other examples and related structures are also disclosed herein.

A method of fabricating radiation sensor dies includes forming a plurality of radiation-sensitive detector elements and a plurality of visible identifiers on at least some of the radiation-sensitive detector elements on a substrate, where each visible identifier is located in a different sub-region of the substrate containing a subset of the radiation-sensitive detector elements, and separating the sub-regions of the substrate from one another to provide a plurality of radiation sensor dies, where the visible identifier on each radiation sensor die uniquely identifies the radiation sensor die with respect to the other radiation sensor dies of the plurality of radiation sensor dies.

A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

A semiconductor device includes a substrate; a semiconductor chip located on the substrate; a sealing resin covering the substrate and the semiconductor chip; and a mottled pattern located at an interface between the sealing resin and at least one of the substrate or the semiconductor chip.

A semiconductor package including a lower substrate, a lower semiconductor chip mounted on the lower substrate, a lower mold layer on the lower substrate and enclosing the lower semiconductor chip, a redistribution layer on the lower mold layer, and a vertical connection terminal around the lower semiconductor chip and connecting the lower substrate to the redistribution layer may be provided. The lower semiconductor chip may include a cognition mark at a top surface thereof. The cognition mark may include a marking pattern having an intaglio shape at the top surface of the lower semiconductor chip, and a molding pattern filling an inner space of the marking pattern. A first material constituting the molding pattern may be the same as a second material constituting the lower mold layer.