The present invention relates to a system and a method for confirming the mounted state of picker mounts. Barcodes are formed on corresponding picker mounts while including information for identifying each type of picker mount. A barcode reader is arranged on one side of a variable picker module so as to sequentially read each barcode of the picker mounts moving in the arrangement direction of pickers while mounted on the pickers. A system controller identifies each position and type of the corresponding picker mounts on the basis of information provided from the barcode reader, and then, compares same with confirmation criteria so as to confirm incorrect mounting and non-mounting of the picker mounts.

A method for securing and verifying semiconductor wafers during fabrication includes receiving a semiconductor wafer after a layer of features has been patterned thereon. At least one security mark is formed at one or more locations embedded within a backside of the semiconductor wafer by implanting an inert species at the one or more locations. At a subsequent point in fabrication and/or after fabrication of the semiconductor wafer has completed the backside of the wafer is inspected for detection of the at least one security mark. If the at least one security mark is not detected at an expected location within the backside of the semiconductor wafer a determination is made that the semiconductor wafer has been compromised.

Devices, systems, and methods are described related to providing nonlinear lithographic seams, such as rectilinear lithographic seams, between adjacent fields of an integrated circuit die. Such nonlinear lithographic seams include lithographic enabling structures formed in co-planar layers with respect to functional structures in functional units of the fields of the integrated circuit die. Providing nonlinear lithographic seams improves layout efficiency of the functional units of the integrated circuit die.

Embodiments described herein may be related to apparatuses, processes, and techniques related to using full stack overlay cell (FSOL) targets within lithography masks and on fabricated layers of a substrate in order to align or to assess the alignment of fabricated layers of the substrate during the substrate manufacturing process. Other embodiments may be described and/or claimed.

A substrate is disclosed. The substrate includes a transparent underlayer, a plurality of signal lines on the transparent underlayer, and a plurality of labels on the transparent underlayer. The plurality of labels respectively correspond to the plurality of signal lines in a one-to-one relationship and are configured to identify the corresponding signal lines, and one of at least two adjacent labels is a forward pattern label, and another one of the at least two adjacent labels is a reverse pattern label.

An electronic device comprising a semiconductor chip which comprises a plurality of structures formed in the semiconductor chip, wherein the semiconductor chip is a member of a set of semiconductor chips, the set of semiconductor chips comprises a plurality of subsets of semiconductor chips, and the semiconductor chip is a member of only one of the subsets. The plurality of structures of the semiconductor chip includes a set of common structures which is the same for all of the semiconductor chips of the set, and a set of non-common structures, wherein the non-common structures of the semiconductor chip of the subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a first portion of the non-common structures and a first portion of the common structures form a first non-common circuit, wherein the first non-common circuit of the semiconductor chips of each subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a second portion of the non-common structures is adapted to store or generate a first predetermined value which uniquely identifies the first non-common circuit, wherein the first predetermined value is readable from outside the semiconductor chip by automated reading means.

Product management and/or prompt defect analysis of a semiconductor device may be carried out without reducing the throughput in assembly and testing. Unique identification information is attached to a plurality of substrates (lead frames) used in manufacturing a semiconductor device (QFP) and to a transport unit for transporting a plurality of substrates, respectively. Identification information (rack ID) of the transport unit and identification information (substrate ID) of the substrate stored into the transport unit are associated with each other. The substrate is taken out from the transport unit set to a loader unit of each manufacturing apparatus and supplied to a processing unit, of the apparatus and in storing the substrate, the processing of which is complete, into a transport unit of an unloader unit of the apparatus, an association between identification information of the transport unit and the identification information of the substrate is checked.

A method includes providing a substrate having substrate terminals and providing a first component having a first terminal and a second terminal. The method includes providing a clip structure having a first clip, a second clip, and a clip connector coupling the first clip to the second clip. The method includes coupling the first clip to the first terminal and a substrate terminal and coupling the second clip to another substrate terminal. The method includes encapsulating the structure and removing a portion of the clip connector. In some examples, the first portion of the clip connector includes a first portion surface, the second portion of the clip connector includes a second portion surface, and the first portion surface and the second portion surface are exposed from a top side of the encapsulant. Other examples and related structures are also disclosed herein.

A marking structure where marking visibility is improved is provided. In a semiconductor device having a marking structure, the marking structure includes: a body for marking having a surface; a first mark group having a first concave portion formed in the surface; a second mark group having a second concave portion formed adjacent to the first concave portion in the surface. The first concave portion and the second concave portion differ in shape so that they may cause light reflection differently. Thus, visibility of the marking structure can be improved.

Provided is a semiconductor structure including an interconnect structure, disposed over a substrate; a pad structure, disposed over and electrically connected to the interconnect structure, wherein the pad structure comprises a metal pad and a dielectric cap on the metal pad, and the pad structure has a probe mark recessed from a top surface of the dielectric cap into a top surface of the metal pad; a protective layer, conformally covering the top surface of the dielectric cap and the probe mark; and a bonding structure, disposed over the protective layer, wherein the bonding structure comprises: a bonding dielectric layer at least comprising a first bonding dielectric material and a second bonding dielectric material on the first bonding dielectric material; and a first bonding metal layer disposed in the bonding dielectric layer and penetrating through the protective layer and the dielectric cap to contact the metal pad.