An inspection system for a semiconductor package includes an inspection apparatus that includes a stage on which the semiconductor package is loaded, and a computer coupled to the inspection apparatus. The semiconductor package may include a first semiconductor chip and a second semiconductor chip on the first semiconductor chip, the computer may provide first identification information about the first semiconductor chip and second identification information about the second semiconductor chip, and the computer may control the inspection apparatus to selectively perform a package test process on one of the first and second semiconductor chips, the one of the first and second semiconductor chips being identified as a good chip based on the first identification information and the second identification information.

A micro-component comprises a component substrate having a first side and an opposing second side. Fenders project from the first and second sides of the component substrate and include first-side fenders extending from the first side and a second-side fender extending from the second side of the component substrate. At least two of the first-side fenders have a non-conductive surface and are disposed closer to a corner of the component substrate than to a center of the component substrate.

A dicing sheet with a protective film forming layer has a substrate film, an adhesive layer, and a protective film forming layer, and at a minimum, the adhesive layer is formed in an area surrounding the protective film forming layer in a planar view, and the substrate film has the following characteristics (a)-(c): (a) the melting point either exceeds 130° C. or the film has no melting point; (b) the thermal contraction rate under conditions of heating at 130° C. for two hours is from −5 to +5%, and (c) the degree of elongation-to-break in the MD direction and the CD direction is at least 100%, and the stress at 25% is no more than 100 MPa.

Methods of protecting semiconductor devices may involve forming trenches in streets between stacks of semiconductor dice on regions of a semiconductor wafer. A protective material may be positioned between the die stacks and in the trenches, after which the wafer is thinned from a side opposite the die stacks to expose the protective material in the trenches. Semiconductor devices comprising stacks of dice and corresponding base semiconductor dice comprising wafer regions are separated from one another by cutting through the protective material along the streets and in the trenches. The protective material covers at least sides of each die stack as well as side surfaces of the corresponding base semiconductor die.

A wafer processing method for dividing a wafer into individual device chips along division lines is disclosed. The wafer processing method includes a back grinding step of grinding the back side of the wafer in the condition where a protective tape is attached to the front side of the wafer, thereby reducing the thickness of the wafer to a predetermined thickness, and a reinforcing insulation seal mounting step of mounting a reinforcing insulation seal capable of transmitting infrared light on the back side of the wafer. The wafer processing method further includes a modified layer forming step of applying a laser beam along each division line to thereby form a modified layer inside the wafer along each division line and a wafer dividing step of applying an external force to the wafer to thereby divide the wafer into the individual device chips along each division line.

In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.

A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

A thermosetting adhesive sheet comprises a thermosetting binder, a transparent filler having an average primary particle diameter from 1 nm to 1000 nm and a colorant; wherein content of the transparent filler is from 30 to 100 pts. mass with respect to 80 pts. mass of the thermosetting binder and content of the colorant is from 0.5 to 3.0 pts. mass with respect to 80 pts. mass of the thermosetting binder; this thermosetting adhesive sheet is applied to a grinding-side surface of a semiconductor wafer and before dicing the semiconductor wafer. Printing using laser marking is thus made clear enabling excellent laser mark visibility and accurate alignment using infrared light.

Systems and methods for visual identification of semiconductor dies are described. In some embodiments, a method may include: receiving a semiconductor wafer having a plurality of dies and printing a unique visual identification mark on each of the plurality of dies. In other embodiments, a method may include receiving an electronic device comprising a die and a package surrounding at least a portion of the die and reading, from the electronic device, a unique visual identification mark that encodes a Cartesian coordinate of the die relative to a reference point on a semiconductor wafer.

Provided is a method for manufacturing a thin SiC wafer by which a SiC wafer is thinned using a method without generating crack or the like, the method in which polishing after adjusting the thickness of the SiC wafer can be omitted. The method for manufacturing the thin SiC wafer 40 includes a thinning step. In the thinning step, the thickness of the SiC wafer 40 can be decreased to 100 μm or less by performing the Si vapor pressure etching in which the surface of the SiC wafer 40 is etched by heating the SiC wafer 40 after cutting out of an ingot 4 under Si vapor pressure.