A position detector includes a detection unit configured to detect light from a first diffraction grating including a first pattern disposed in a first direction, and light from a second diffraction grating including a second pattern disposed in the first direction, and a control unit configured to obtain a relative position between the first and the second diffraction gratings based on the light detected by the detection unit. The position detector has a third pattern formed in a second direction different from the first direction at edges of the first pattern of the first diffraction grating, the third pattern has a width smaller than a width of the first pattern of the first diffraction grating.

A device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a gate electrode over the gate dielectric. The gate electrode has a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness. The device further includes a source/drain region on a side of the gate electrode with the source/drain region extending into the semiconductor substrate, and a device isolation region. The device isolation region has a part having a sidewall contacting a second sidewall of the source/drain region to form an interface. The interface is overlapped by a joining line of the firs portion and the second portion of the gate electrode.

In a system for aligning at least two semiconductor structures for coupling, an alignment device includes a mounting structure having at least first and second opposing portions. The alignment device also includes a first mounting portion movably coupled to the first portion of the mounting structure, the first mounting portion configured to couple to a first surface of a first semiconductor structure. The alignment device additionally includes a second mounting portion movably coupled to the second portion of the mounting structure, the second mounting portion configured to couple to a second surface of a second semiconductor structure. The alignment device further includes one or more imaging devices disposed above at least one of the first and second mounting portions of the alignment device, the imaging devices configured to capture and/or or detect alignment marks in at least the first semiconductor structure. A corresponding method for aligning two or more semiconductor structures for coupling is also provided.

Examples of techniques for an integrated wafer-level processing system are disclosed. In one example implementation according to aspects of the present disclosure, an integrated wafer-level processing system includes a memory wafer and a processing element connected to the memory wafer via a data connection.

A semiconductor package includes a substrate having at least one recessed portion, a semiconductor device located on a surface of the substrate, the surface having the at least one recessed portion, and a resin insulating layer covering the semiconductor device.

A chip singulation method includes, in stated order: forming a surface supporting layer on an upper surface of a wafer; thinning the wafer from the undersurface to reduce the thickness to at most 30 μm; removing the surface supporting layer from the upper surface; forming a first metal layer and subsequently a second metal layer on the undersurface of the wafer; applying a dicing tape onto an undersurface of the second metal layer; applying, onto the upper surface of the wafer, a process of increasing hydrophilicity of a surface of the wafer; forming a water-soluble protective layer on the surface of the wafer; cutting the wafer, the first metal layer, and the second metal layer by irradiating a predetermined region of the upper surface of the wafer with a laser beam; and removing the water-soluble protective layer from the surface of the wafer using wash water.

The disclosure relates to integrated circuit (IC) structures and fabrication techniques. Methods according to the disclosure can include: providing a precursor structure including: a first inter-metal dielectric (IMD); a barrier dielectric positioned on the first IMD; forming an insulator on the barrier dielectric of the precursor structure, wherein an upper surface of the insulator includes a first trench and a second trench laterally separated from the first trench; forming an alignment marker over the precursor structure by filling the first trench with a first refractory metal film; forming a first metal-insulator-metal (MIM) electrode by filling the second trench with the first refractory metal film; recessing the insulator without exposing an upper surface of the barrier dielectric; forming a MIM dielectric layer on the insulator; and forming a second MIM electrode on the MIM dielectric layer, such that the second MIM electrode overlies a portion of the first MIM electrode.

A lead frame strip with corrugated saw street metal where the corrugated saw street metal is comprised of a partial thickness of the lead frame strip metal. A lead frame strip with corrugated saw street metal where the corrugated saw street metal is comprised of a half thickness of the lead frame strip metal.

A method for measuring overlay at a semiconductor device on which circuit patterns are formed by a plurality of exposure processes is characterized in including an image capturing step for capturing images of a plurality of areas of the semiconductor device, a reference image setting step for setting a reference image based on a plurality of the images captured in the image capturing step, a difference quantifying step for quantifying a difference between the reference image set in the reference image setting step and the plurality of images captured in the image capturing step, and an overlay calculating step for calculating the overlay based on the difference quantified in the difference quantifying step.

A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.