A glass substrate is laminated with a substrate containing silicon to thereby form a laminated substrate. The glass substrate has a concave surface and a convex surface and has one or more marks that distinguish between the concave surface and the convex surface.

Disclosed herein is a wafer jig with an identification mark for use in inspecting the function of an identification mark reading mechanism for reading an identification mark on a device wafer. The wafer jig includes a wafer piece cut from a region of a device wafer where an identification mark is formed, and a circular plate having the same diameter as the device wafer. The wafer piece is fixed to the circular plate such that the identification mark on the wafer piece is positionally aligned with the identification mark on the device wafer.

A laser processing apparatus has a control unit including an inspection modified layer former detecting a provisional orientation flat of a bare wafer and applying a laser beam of a predetermined output power level to the bare wafer depending on the direction of the provisional orientation flat thereby to form a modified layer for detecting the crystal orientation closely to an outer edge of the bare wafer, and a crack detector detecting a crack extending from the modified layer toward a Y-axis and an exposed surface of the bare wafer, providing the modified layer extends along an X-axis in an image captured of the modified layer. If the crack detector detects no crack, the control unit determines the modified layer with no crack extending therefrom as extending parallel to the crystal orientation of the bare wafer.

A wafer processing method includes preparing a holding table having a blade clearance portion formed therein so as to correspond to a notch of a wafer, holding the wafer by the holding table so as to make the notch of the wafer correspond to the blade clearance portion of the holding table, reducing the diameter of the wafer by cutting the wafer by a cutting blade along an outer peripheral edge of the wafer in a state in which an end of the cutting blade is positioned below the holding surface of the holding table and therefore removing at least a part of the notch portion, and forming a second notch in the wafer by cutting the wafer in a thickness direction by the cutting blade along the blade clearance portion of the holding table.

A method for determining overlay measurements includes orienting a wafer to align portions of lines of a pattern of an overlay mark with a direction in which a source emits light at the wafer and align other portions of the lines of the pattern to extend in a direction perpendicular to the direction in which the illumination source emits light at the wafer. The method includes capturing at least one image of the wafer via an imager sensor. The method also includes determining contrasts of regions of the overlay mark and determining a location of the overlay mark. Overlay marks include a pattern defining an array of columns. Each column includes a set of continuous lines oriented parallel to each other and extending in a first direction within a first region of a column and extending in a second different direction in a second region of the column.

Methods and systems allow a user or operator to easily create cyber-training environments for use in a cyber-training system. In one embodiment, the environments are configured as missions. The missions may have a plurality of features, such as training objectives, a mission storyline, a mission order and mission objectives, relative to a mission environment. The mission environment comprises a virtual environment, such as defined by a virtual network having virtual machines or devices.

In an embodiment, a semiconductor wafer includes a front surface, a plurality of active component positions, and at least one composite alignment mark arranged on the front surface and indicating a unique orientation of the semiconductor wafer. The composite alignment mark includes a first portion that has at least one raised section formed of a first material and a second portion that is positioned laterally adjacent the first portion. The second portion has at least one raised section formed of a second material that is different form the first material.

Some embodiments include an integrated assembly having a base supporting first circuitry and first conductive lines. The first conductive lines extend along a first direction and are associated with the first circuitry. A deck is over the base and supports an array of memory cells and second conductive lines which are associated with the array of memory cells. The second conductive lines extend along a second direction which is substantially orthogonal to the first direction. Vertical interconnects extend from the deck to the base and couple the first conductive lines to the second conductive lines. Each of the vertical interconnects couples one of the first conductive lines to one of the second conductive lines. Each of the second conductive lines is coupled with only one of the first conductive lines.

A processing apparatus includes a wafer carrying-out unit, a wafer table that supports a wafer carried out, a frame carrying-out unit, a frame table that supports an annular frame carried out, a tape sticking unit that sticks a tape to the frame, a tape-attached frame conveying unit, a tape pressure bonding unit that executes pressure bonding of the tape of a tape-attached frame to a back surface of the wafer, a frame unit carrying-out unit, and a beveled part removing unit that cuts and removes, in a ring manner, a beveled part formed in an outer circumferential surplus region from the wafer of a frame unit.

A processing apparatus includes a wafer carrying-out unit, a wafer table that supports a wafer carried out, a frame carrying-out unit, a frame table that supports an annular frame carried out, a tape sticking unit that sticks a tape to the annular frame, a tape-attached frame conveying unit, a tape pressure bonding unit that executes pressure bonding of the tape of a tape-attached frame to the back surface of the wafer, a frame unit carrying-out unit, and a reinforcing part removing unit that cuts and removes a ring-shaped reinforcing part from the wafer of a frame unit.