Patent classifications
H01L2924/01007
Silver bonding wire for semiconductor device containing indium, gallium, and/or cadmium
The present invention provides a bonding wire which can satisfy bonding reliability, spring performance, and chip damage performance required in high-density packaging. A bonding wire contains one or more of In, Ga, and Cd for a total of 0.05 to 5 at %, and a balance being made up of Ag and incidental impurities.
Silver bonding wire for semiconductor device containing indium, gallium, and/or cadmium
The present invention provides a bonding wire which can satisfy bonding reliability, spring performance, and chip damage performance required in high-density packaging. A bonding wire contains one or more of In, Ga, and Cd for a total of 0.05 to 5 at %, and a balance being made up of Ag and incidental impurities.
Tooling for coupling multiple electronic chips
A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface.
Method for processing a die
In various embodiments, a die is provided. The die may include a die body, and at least one of a front side metallization structure on a front side of the die body and a back side metallization structure on a back side of the die body such that the die is plane or includes a positive radius of curvature at a die attach process temperature range.
Pressure sensor device including-fluorinated gel protective member disposed on a protective film
In aspects of the invention, a sensor unit is stored in a recessed sensor mount portion formed in a resin case. The sensor unit can be formed so that a semiconductor pressure sensor chip is joined to one side of a glass pedestal, and the other side of the glass pedestal is die-bonded to the bottom of the sensor mount portion through an adhesive. An electrode pad on the semiconductor pressure sensor chip is electrically connected through a bonding wire to a lead terminal for leading externally that pierces through the resin case and is integrally insert-molded therein. An entire surface of the sensor unit, an exposed part of the lead terminal internally-located in the resin case, the bonding wire, and an exposed part of an inner wall of the resin case can be coated with the protective film composed of a poly(p-xylylene)-family polymer including fluorine.
Pressure sensor device including-fluorinated gel protective member disposed on a protective film
In aspects of the invention, a sensor unit is stored in a recessed sensor mount portion formed in a resin case. The sensor unit can be formed so that a semiconductor pressure sensor chip is joined to one side of a glass pedestal, and the other side of the glass pedestal is die-bonded to the bottom of the sensor mount portion through an adhesive. An electrode pad on the semiconductor pressure sensor chip is electrically connected through a bonding wire to a lead terminal for leading externally that pierces through the resin case and is integrally insert-molded therein. An entire surface of the sensor unit, an exposed part of the lead terminal internally-located in the resin case, the bonding wire, and an exposed part of an inner wall of the resin case can be coated with the protective film composed of a poly(p-xylylene)-family polymer including fluorine.
RESISTIVE ELEMENT AND METHOD OF MANUFACTURING THE RESISTIVE ELEMENT
A resistive element includes: a semiconductor substrate; a first insulating film deposited on the semiconductor substrate; a resistive layer deposited on the first insulating film; a second insulating film deposited to cover the first insulating film and the resistive layer; a first electrode deposited on the second insulating film and electrically connected to the resistive layer; a relay wire deposited on the second insulating film without being in contact with the first electrode, and including a resistive-layer connection terminal electrically connected to the resistive layer and a substrate connection terminal connected to the semiconductor substrate with an ohmic contact; and a second electrode deposited on a bottom side of the semiconductor substrate, wherein a resistor is provided between the first electrode and the second electrode.
RESISTIVE ELEMENT AND METHOD OF MANUFACTURING THE RESISTIVE ELEMENT
A resistive element includes: a semiconductor substrate; a first insulating film deposited on the semiconductor substrate; a resistive layer deposited on the first insulating film; a second insulating film deposited to cover the first insulating film and the resistive layer; a first electrode deposited on the second insulating film and electrically connected to the resistive layer; a relay wire deposited on the second insulating film without being in contact with the first electrode, and including a resistive-layer connection terminal electrically connected to the resistive layer and a substrate connection terminal connected to the semiconductor substrate with an ohmic contact; and a second electrode deposited on a bottom side of the semiconductor substrate, wherein a resistor is provided between the first electrode and the second electrode.
Method for low temperature bonding and bonded structure
A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO.sub.2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
Cu ALLOY CORE BONDING WIRE WITH Pd COATING FOR SEMICONDUCTOR DEVICE
A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof, and the boding wire contains one or more elements of As, Te, Sn, Sb, Bi and Se in a total amount of 0.1 to 100 ppm by mass. The bonding longevity of a ball bonded part can increase in a high-temperature and high-humidity environment, improving the bonding reliability. When the Cu alloy core material further contains one or more of Ni, Zn, Rh, In, Ir, Pt, Ga and Ge in an amount, for each, of 0.011 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 170 C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves.