A stacked-waveguide substrate includes: a body configured to include a first dielectric-substrate, a second dielectric-substrate, and a third dielectric-substrate which are stacked in this order; a first conductor-pattern configured to be formed on a bottom surface of the first dielectric-substrate; a second conductor-pattern configured to be formed on a top surface of the third dielectric-substrate in a position corresponding to the first conductor-pattern; a first conductor-film configured to be located at an interface between the first dielectric-substrate and the second dielectric-substrate, and to have a first opening which faces the first conductor-pattern; a second conductor-film configured to be located at an interface between the second dielectric-substrate and the third dielectric-substrate, and to have a second opening which faces the second conductor-pattern; a first wiring line configured to cross the first opening to the first conductor-pattern; and a second wiring line configured to cross the second opening to the second conductor-pattern.

A stacked-waveguide substrate includes: a body configured to include a first dielectric-substrate, a second dielectric-substrate, and a third dielectric-substrate which are stacked in this order; a first conductor-pattern configured to be formed on a bottom surface of the first dielectric-substrate; a second conductor-pattern configured to be formed on a top surface of the third dielectric-substrate in a position corresponding to the first conductor-pattern; a first conductor-film configured to be located at an interface between the first dielectric-substrate and the second dielectric-substrate, and to have a first opening which faces the first conductor-pattern; a second conductor-film configured to be located at an interface between the second dielectric-substrate and the third dielectric-substrate, and to have a second opening which faces the second conductor-pattern; a first wiring line configured to cross the first opening to the first conductor-pattern; and a second wiring line configured to cross the second opening to the second conductor-pattern.

A method produces a semiconductor apparatus for a quantum computer. The apparatus includes: a semiconductor substrate; a quantum computer device formed on the semiconductor substrate; and a peripheral circuit formed on the semiconductor substrate and connected to the quantum computer device. The apparatus is to be used as a quantum computer. The method includes: a step of forming the quantum computer device and the peripheral circuit on the semiconductor substrate; and a step of deactivating a carrier in the semiconductor substrate by irradiation of a particle beam to at least a formation part for the quantum computer device and a formation part for the peripheral circuit in the semiconductor substrate. The method for producing a semiconductor apparatus for a quantum computer can produce a semiconductor apparatus for a quantum computer having excellent 3HD characteristics.

A waveguide includes: a substrate; a first ground wire; a second ground wire; a signal wire; and a compensation structure. The first ground wire, the second ground wire, and the signal wire are disposed on the substrate at intervals, and the signal wire is located between the first ground wire and the second ground wire. The compensation structure is configured to contact at least one of the substrate, the first ground wire, the second ground wire, or the signal wire; and the compensation structure comprises a superconducting material.

Methods, apparatuses, and devices for quantum chip preparation include acquiring a coplanar waveguide in a quantum chip; and establishing a connecting bridge on the coplanar waveguide using a bonding machine, wherein the connecting bridge is configured to connect a first reference ground and a second reference ground located on two sides of the coplanar waveguide to change the chip electromagnetic resonance frequency. A quantum chip includes a transmission line configured for signal transmission; and a resonant cavity coupled to the transmission line and configured to regulate an operating state of qubits on the quantum chip, wherein the transmission line and the resonant cavity are both composed of a coplanar waveguide, the coplanar waveguide is provided with a connecting bridge, and the connecting bridge is configured to connect a first reference ground and a second reference ground on two sides of the coplanar waveguide to change the chip electromagnetic resonance frequency.

A packaging structure, a method of manufacturing a packaging structure, and a quantum processor include a substrate; a coplanar waveguide including a first ground wire, a second ground wire, and a signal wire, wherein the first ground wire, the second ground wire, and the signal wire are disposed on a surface of the substrate at intervals, and the signal wire is located between the first ground wire and the second ground wire; an air bridge including a first end connected with the first ground wire and a second end connected with the second ground wire, wherein a gap exists between the air bridge and a surface of the signal wire away from the substrate; and a compensation structure located on the surface of the substrate.

A printed circuit board includes: a conductor plate below the inner dielectric layer; some vias through the inner dielectric layer, bonded to the conductor plate, centered at respective points on an upper surface of the conductor plate; a ground conductor above the inner dielectric layer, bonded to the vias, extending outwardly from any quadrangle with vertices being the nearest four points of the points; an electromagnetic resonance plate above the inner dielectric layer and inside the quadrangle, electrically connected to the ground conductor and the vias with a portion other than a protruding outer edge serving as a junction; an upper dielectric layer above the electromagnetic resonance plate; and a differential transmission line pair composed of a pair of strip conductors overlapping with the electromagnetic resonance plate, above the upper dielectric layer. The conductor plate and the vias constitute an electromagnetic field confinement structure.

Systems and methods for isolating radio frequency (RF) signals in high frequency circuit assemblies, including but not limited to 5G communication systems, are provided. The circuit assemblies include an RF suppression structure, which can be in the form of a low ohm resistor, that extends across a transmission line, and that has contacts that are electrically joined to a ground plane. Alternatively or in addition, the circuit assemblies include a low ohm resistor that extends over a transition between a signal via and an end of a transmission line, and that has contacts that are electrically joined to a ground plane. A circuit assembly as disclosed herein can further include multiple low ohm resistors spaced apart from one another by a distance that is a fraction of a wavelength of a highest frequency signal carried by the transmission line.

Antenna and/or waveguide assemblies for vehicles, such as RADAR sensor antenna assemblies, along with associated signal confinement structures. In some embodiments, the assembly may comprise an antenna block defining one or more waveguides. A conductive layer may be coupled to the antenna block to form, at least in part, a wall of the waveguide. The assembly may comprise one or more periodic structures that may be operably coupled to the waveguide, each of which may comprise a first elongated opening and a first series of repeated slots extending at least substantially transverse to the first elongated opening, wherein each of the first series of repeated slots is spaced apart from an adjacent slot in the first series of repeated slots along the first elongated opening.

Provided is a structure configured to electrically connect multi-layer dielectric waveguides, each including a dielectric waveguide formed of conductor patterns and vias in a laminating direction of the multi-layer dielectric substrate, in which the vias for forming part of a waveguide wall of each of the dielectric waveguides are arranged in a staggered pattern in the multi-layer dielectric substrate side having choke structures formed so as to electrically connect the waveguides to each other.