A modulation technique is described in which a controller modulates the output AC voltages to introduce an offset to the phase that is most positive or most negative such that the phase is clamped to the +dc supply when the respective phase is most positive and to the −dc supply rail when most negative. The offset is provided by introducing a common mode component voltage to all of the phases over a plurality of output angle segments. In order to reduce the Noise Vibration and Harshness (NVH) and EMI, the common mode component voltage amplitude is varied over the output angles within the respective segment between a minimum and a maximum in order to control a slew rate of the rising or falling edges of the three phase AC output voltages.

An embodiment provides a closed loop active gate driver configured to drive a switch for an inductive load and including a feedback loop, the feedback loop configured to sample a repetitive output waveform of the inductive load, the output waveform having a plurality of repetitive cycles and the feedback loop configured to sample the output waveform using a sampling rate that is lower than a sampling rate required for characterizing the output waveform, sample points acquired in cycles of the plurality of cycles are acquired at different time points during the cycles and wherein a representation of the output waveform is reconstructed using the sample points.

A Power Over Data Lines (PoDL) system includes Power Sourcing Equipment (PSE) supplying DC power and differential Ethernet data over a single twisted wire pair to a Powered Device (PD). Due to start-up perturbations, PD load current variations, and other causes, dV/dt noise is introduced in the power signal. Such noise may be misinterpreted as data unless mitigated somehow. Rather than increasing the values of the passive filtering components conventionally used for decoupling/coupling the power and data from/to the wire pair, active circuitry is provided in the PSE, PD, or both to limit dV/dt in the power signal. Such circuitry may be implemented on the same chip as the PSE controller or PD controller. Therefore, the sizes of the passive components in the decoupling/coupling networks may be reduced.

A gate drive control circuit is provided that charges a gate voltage of a power switch transistor during a power switch transistor on-time period. During a first portion of the on-time period, the gate drive control circuit charges the gate voltage through a relatively-low resistance. During a second portion of the on-time period, the gate drive control circuit charges the gate voltage through a relatively-high resistance. Finally, during a third portion of the on-time period, the gate drive control circuit charges the gate voltage through another relatively-low resistance.

A drive adjustment circuit for a power semiconductor element includes a differentiating circuit to differentiate a gate voltage of a power semiconductor element, a power supply to generate a comparison reference voltage, a comparator having a first input terminal connected to the differentiating circuit and a second input terminal receiving the comparison reference voltage, and a voltage adjusting circuit to adjust a gate voltage of the power semiconductor element based on an output of the comparator.

Examples may include an apparatus including a circuit coupled between a supply line, a return line, and a terminal. The circuit may provide an oscillating signal to the terminal. The circuit may include a first switch to couple the supply line with the terminal. The circuit may also include a second switch to couple the return line with the terminal. The circuit may also include a first inductor coupled between the first switch and the terminal. The circuit may also include a second inductor coupled between the second switch and the terminal. The circuit may also include a first diode coupled between the return line and an internal node of the first switch and the first inductor. The circuit may also include a second diode coupled between the supply line and an internal node of the second switch and the second inductor. Related systems and methods are also disclosed.

A switching power converter architecture that is efficient across its entire power range, regardless of load level, by partitioning the power devices into segments for optimal gate drive and providing a local variable-voltage driver for each power device segment. Power device segments may be selectively enabled or disabled based on the level of power to be delivered to a load. In addition, an adaptive gate drive scheme enables dynamic control of the R.sub.ON and Q.sub.G values for each power converter device so that the power devices may operate at the lowest R.sub.ON value at or near maxi-mum power levels for reduced conduction losses, at the lowest R.sub.ON×Q.sub.G product value at mid-level loads for peak efficiency, and at the lowest Q.sub.G value at light loads for reduced switching losses.

A control circuit for a switched-mode power converter to generate a control signal for controlling switching transistors in the power converter is disclosed. The control circuit includes: a comparator; a ramp compensation circuit for producing and applying a ramp compensation signal to a first or second input of the comparator; an on-time generation circuit to generate an on-time timer signal; and a control signal generation circuit to generate, based on the comparison signal and the on-time timer signal, the control signal for controlling the switching transistors in the power converter. The ramp compensation signal output from the ramp compensation circuit is configured with: a first slope during an inductor demagnetization interval in operation of the power converter in CCM and a second slope during an inductor demagnetization interval and a zero-current interval in operation of the power converter in DCM, the first slope is greater than the second slope.

A semiconductor device according to an embodiment includes: a first transistor having a first electrode, a second electrode, and a first control electrode, the first transistor performing a switching operation; a second transistor having a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode, the second transistor performing an analog operation; and a third transistor having a fifth electrode electrically connected to the fourth electrode, a sixth electrode, and a third control electrode.

The switching power source device obtains a desired DC voltage by controlling the current flowing through a coil by turning on and off a switching element by a PWM control. In the PWM ON period to turn on the switching element by the PWM control, the switching power source device is enabled to switch the switching element by a first pulse signal whose cycle is shorter than the PWM cycle and whose pulse width is gradually increased, in a first period just after the start of the PWM ON period. Further, the switching power source device is enabled to switch the switching element by a PWM signal based on the PWM control after the first period in the PWM ON period has elapsed. According to this approach, it is possible to reduce the harmonic noise.