A class-D amplifier including a pulse width modulator including an input configured to receive a first signal based on an input signal, and an output configured to generate a pulse width modulated (PWM) signal; an H-bridge including an input coupled to an output of the pulse width modulator and an output coupled to a load, wherein the H-bridge is configured to generate an output signal across the load based on the PWM signal; and a deadtime compensation circuit coupled to the H-bridge, wherein the deadtime compensation circuit is configured to compensate for deadtime distortion in the output signal. The deadtime compensation circuit may be a feedback circuit between an output of the H-bridge and an input of the pulse width modulator, a pulse modification circuit at the output of the pulse width modulator, or an offset signal generating circuit providing an offset signal to the pulse width modulator.

A voltage measurement device for pulse-width modulation (PWM) signals is provided, which includes a conversion circuit and a processing circuit. The conversion circuit receives a first PWM signal and a second PWM signal from a motor driving device, and converts the first PWM signal and the second PWM signal into the absolute value signal and the polarity signal of the line-to-line voltage signal between the first PWM signal and the second PWM signal. The processing circuit converts the polarity signal and the absolute value signal into a first integral signal and a second integral signal, and reconstructs the line-to-line voltage signal according to the first integral signal and the second integral signal so as to obtain the reconstructed voltage signal of the line-to-line voltage signal.

An apparatus for enabling an inverter to switch between modes includes: a first inverter unit; a second inverter unit; a load connected between the first inverter unit and the second inverter unit; a mode switching unit connected between the load and the second inverter unit; and a control unit configured to drive the load in a one-stage inverter mode or a two-stage inverter mode by performing control that turns on or off the mode switching unit. In particular, when an inverter switches between modes, the control unit performs mode switching in accordance with correct mode switching timing synchronization for PWM signal output.

An isolated bus inverter system including inverter circuits and a controller. The inverter circuits include a switching array to provide a polyphase alternating current (AC) signal to an output. Each of the inverter circuits includes an energy source isolated from the other inverter circuits of the inverter circuits or a reference isolated from the other inverter circuits of the inverter circuits. The controller is configured to generate timing signals for the inverter circuits to generate the AC signals for the output based on DC signals received from one or more rectifier circuits.

A motor control device includes a motor drive circuit and a microcomputer that controls the drive circuit. The microcomputer generates a control signal on the basis of duty command values Du, Dv, and Dw to control the drive circuit. The microcomputer includes a dead time compensation section that corrects the duty command values Du, Dv, and Dw on the basis of dead time compensation values Ddu, Ddv, and Ddw. The dead time compensation section includes a basic compensation value computation section that computes a basic compensation value Dd as a fundamental value of the dead time compensation values Ddu, Ddv, and Ddw, and a filter section that performs a filtering process corresponding to a low-pass filter on the basic compensation value Dd. The dead time compensation section sets the dead time compensation values Ddu, Ddv, and Ddw on the basis of an output value α from the filter section.

A switching converter circuit, which switches one terminal of an inductor to different voltages, includes a high side MOSFET, a low side MOSFET, and a driver circuit which includes a high side driver, a low side driver, and a dead time control circuit. According to an output current, The dead time control circuit adaptively delays a low side driving signal to generate a high side enable signal for enabling the high side driver to generate a high side driving signal according to a pulse width modulation (PWM) signal; and/or adaptively delays the high side driving signal to generate a low side enable signal for enabling the low side driver to generate the low side driving signal according to the PWM signal, so as to adaptively control a dead time in which the high side MOSFET and the low side MOSFET are both not conductive.

A dead time control method (100) comprising the steps of: converting the DC link voltage, output current and output voltage to digital values with an ADC (Analog to Digital converter) (102); calculating the hysteresis band for adaptive hysteresis current control using the values read by the ADC and updating the band value via recalculating it at each sampling time (103); calculating the IrefH and IrefL values using the hysteresis band and Iref (103a); generating the PWM signal by hysteresis current control (104), generating two auxiliary control signals as VP, VN (105); in the region where VP=1 and VN=0, applying of the drive signal of T.sub.1 without setting dead time wherein T.sub.1 is the conduction duration of an upper switch, and not applying the drive signal of T.sub.2 wherein T.sub.2 is the turn off duration of said upper switch and is the conduction duration of a lower switch (106).

Disclosed is a method for deadtime optimization in a half-bridge switch or full-bridge switch wherein high-side and low-side switches comprise GaN transistors; a circuit for implementing the method; and a power switching system comprising a GaN half-bridge or a GaN full-bridge and a deadtime optimization system. The circuit comprises a drain current bump filter for generating a current charge output; and circuit elements for comparing the current charge output to a reference current charge C.sub.oss and generating a deadtime adjust signal. The deadtime adjust signal may be used to adjust deadtime to reduce or minimize deadtime, and deadtime losses, while avoiding cross-conduction.

A motor driver is provided, which includes a control circuit, a first transistor, a first comparison circuit, a second transistor and a load. The control circuit includes a first output terminal and a second output terminal; the first output terminal outputs a first control signal; the second output terminal outputs a second control signal whose phase is inverse to the phase of the first control signal. The gate of the first transistor receives the first control signal. The first comparison circuit compares the gate-source voltage with a reference voltage to generate a first comparison signal. When the first comparison signal shows that the first control signal is reduced to be lower than the reference voltage, the second control signal generated by the second output terminal is transmitted to the gate of the second transistor.

Embodiments of the present application disclose a multi-level inverter clamping modulation method and apparatus, and an inverter. Switching elements of an inverter are controlled when an output voltage of the inverter crosses zero, and switching elements in each inverter bridge arm of an active clamp multi-level inverter include an internal tube, an external tube, and a clamping tube. The internal tube and the external tube are connected in series between a positive bus and a negative bus, the clamping tube is connected between a common terminal of the internal tube and the external tube and a bus, the internal tube is a low-frequency switching element, and the external tube and the clamping tube are high-frequency switching elements.