A circuit includes a polar transmitter to generate a radio frequency output from amplitude and phase signal components. The polar transmitter includes an amplifier to combine amplitude and phase signal components. A processor is coupled to the polar transmitter to provide the amplitude and phase signal components. The processor includes: a digital modulation circuit to generate a modulated digital signal including in-phase and quadrature signal components and a correction circuit to calculate and apply a complex digital offset for local oscillator feedthrough of the amplifier. The complex digital offset includes an in-phase offset correction factor and a quadrature offset correction factor.

A reduced-complexity Internet of Things sensor is disclosed. An example apparatus comprises memory storing one or more sensor event messages, a radio configured to determine a sensor event, a counter configured to output incremental counter states, and a control circuitry. The control circuitry may be in communication with the memory, the radio, and counter, and the sensor. The control circuitry may be configured to determine, based on the sensor event, a select sensor event message of the one or more sensor event messages. The control circuitry may be further configured to output, via the radio signal, a packet comprising the select event message and an indication of a counter state associated with the sensor event message.

This disclosure provides systems, methods, and devices for wireless communication that support reconfiguring degeneration components in a converged RF transceiver supporting carrier aggregation across sub-6 GHz frequency bands and mmWave frequency bands. In a first aspect, an apparatus includes an input port configured to receive a mixer input signal; a first mixer forming at least a portion of an HRM mixer and coupled to the input port; a first configurable degeneration component of a first processing path coupled between the input port and the first mixer; and a controller coupled to the first degeneration component, wherein the controller is configured to control a first aspect of a first degeneration component. Other aspects and features are also claimed and described.

The present disclosure provides a mixer circuit, a transmitter, and a communication device. The mixer circuit comprises an I-channel digital-to-analog converter, a Q-channel digital-to-analog converter, a low-pass filter, and a passive quadrature mixer, wherein the low-pass filter comprises an active device, so that an output admittance of the mixer circuit contains conductance dependent of frequency. The consistency between the gains of the mixer circuit at the upper sideband and the lower sideband can be improved.

An apparatus (7) for down-converting a sampled signal comprises a processing system (206) configured to apply a mixing-and-combining operation repeatedly to successive sub-sequences of N input samples, X, representative of a signal and having an initial sampling rate, M, to generate a sequence of output samples, Y, having an output rate, T, lower than the initial sampling rate M. The sub-sequences of the N input samples, X, are spaced at intervals that correspond to the output rate M. The mixing-and-combining operation generates a respective output sample Y from each sub-sequence, where Y depends on a set of products of the input samples X of the sub-sequence with respective values derived from a periodic mixing signal having a mixing frequency.

An electronic device may include wireless circuitry with a baseband processor, a transceiver, a front-end module, and an antenna. The transceiver may include mixer circuitry. The mixer circuitry may include switches controlled by oscillator signals. The mixer circuitry may also include oscillator phase noise cancelling capacitors controlled by inverted oscillator signals. Operated in this way, the mixer circuitry exhibits improved noise figure performance.

A circuit for subharmonic detection includes in-phase and quadrature mixers, first and second filters, and a processing circuit. The in-phase mixer has a first mixer input and a first mixer output. The quadrature mixer has a second mixer input and a second mixer output, the first mixer input coupled to the second mixer input. The first filter circuit has a first filter input and a first filter output, the first filter input coupled to the first mixer output. The second filter circuit has a second filter input and a second filter output, the second filter input coupled to the second mixer output. The processing circuit has a first input and a second input, the first input of the processing circuit coupled to the first filter output, the second input of the processing circuit coupled to the second filter output. The processing circuit is configured to detect a subharmonic component of a wave at the first mixer input and the second mixer input using a first direct current (DC) component at the first input of the processing circuit and a second DC component at the second input of the processing circuit.

A circuit for suppressing undesired sub-harmonics includes a plurality of mixers, wherein the plurality of mixers are connected in parallel; a plurality of local oscillator signals (LO), wherein each of the plurality of LOs is associated with one of the plurality of mixers; an input to receive a plurality of phases of a driving clock, wherein each of the plurality of phases is a sub-harmonic of the driving clock, and wherein each phase of the driving clock is distributed to one of the plurality of mixers; wherein the plurality of mixers are configured to suppress one or more of the plurality of phases of the driving clock and amplify a desired phase of the driving clock.

A circuit for subharmonic detection includes in-phase and quadrature mixers, first and second filters, and a processing circuit. The in-phase mixer has a first mixer input and a first mixer output. The quadrature mixer has a second mixer input and a second mixer output, the first mixer input coupled to the second mixer input. The first filter circuit has a first filter input and a first filter output, the first filter input coupled to the first mixer output. The second filter circuit has a second filter input and a second filter output, the second filter input coupled to the second mixer output. The processing circuit has a first input and a second input, the first input of the processing circuit coupled to the first filter output, the second input of the processing circuit coupled to the second filter output. The processing circuit is configured to detect a subharmonic component of a wave at the first mixer input and the second mixer input using a first direct current (DC) component at the first input of the processing circuit and a second DC component at the second input of the processing circuit.

A reduced-complexity Internet of Things sensor is disclosed. An example apparatus comprises memory storing one or more sensor event messages, a radio configured to determine a sensor event, a counter configured to output incremental counter states, and a control circuitry. The control circuitry may be in communication with the memory, the radio, and counter, and the sensor. The control circuitry may be configured to determine, based on the sensor event, a select sensor event message of the one or more sensor event messages. The control circuitry may be further configured to output, via the radio signal, a packet comprising the select event message and an indication of a counter state associated with the sensor event message.