Patent classifications
H03D7/165
Variable duty-cycle multi-standard mixer
An adjustable mixer is disclosed that is capable of operating in different modes in order to satisfy the mixing requirement of multiple radio access technologies (RATs). The adjustable mixer includes a LO signal generating portion and a mixing portion. Depending on the mixing requirements of the RAT, the adjustable mixer can operate in any one of multiple modes, each mode having a specific configuration for the LO signal generating portion and the mixing portion. The LO signal generating portion generates a LO signal having a particular duty cycle, depending on the selected mode, for use by the mixing portion. The mixing portion has an adjustable circuit configuration that can be dynamically reconfigured based on the selected mode, and which allows the mixing portion to successfully mix received signals using the corresponding LO signals generated by the LO signal generating portion.
Ultra-wide band frequency offset estimation systems and methods for analog coherent receivers
Described herein are systems and methods that allow for correcting a residual frequency offset in the GHz frequency range by using low-complexity analog circuit implementations of a broad-band frequency detector that comprises two analog polyphase filters in a dual configuration. Each filter comprises an RC network of cross-coupled capacitors that facilitate filters with opposite passbands and opposite stop-bands. In various embodiments, the outputs of the two filters are combined to obtain power metrics that when subtracted from each other, deliver a measure of the imbalance between the positive and negative halves of a frequency spectrum. Since the measure is substantially proportional to a frequency offset within a linear range spanning 5 GHz or more, the polyphase filters may be used in a broad-band frequency detector that, based on the measure, adjusts the frequency offset.
Signal mixing circuit device and receiver
A signal mixing circuit device and a receiver are disclosed, the signal mixing circuit device comprising first to fourth mixers, first and second signal amplifying circuits, a signal strength detector, a controller and an attenuator. A signal strength value for the output from the first signal amplifying circuit is detected using the signal strength detector. If the signal strength value is less than a first threshold, a high-gain path is initiated, so that noises respectively input to the first and second mixers together with local oscillator signals are eliminated by the fourth and third mixers respectively, thereby ensuring a high signal-to-noise ratio. If the signal strength value is greater than a second threshold, a low-gain path is initiated, which partially reuses the circuit of the high-gain path, thereby effectively reducing the overall circuit area and decreasing chip cost and power consumption.
Software defined radio (SDR) filter relaxation technique for multiple-input and multiple-output (MIMO) and large antenna array (LAA) applications
An example method of operating a radio system includes receiving, over a receiver-path, an RF input signal from an antenna, and converting the RF input signal to fall within a pre-defined frequency range using a local oscillation signal. The method further includes processing the converted input signal with a standard filter. In some examples, the method further includes generating the local oscillation signal in a transmitter path of the radio system.
LO LEAKAGE SUPPRESSION IN FREQUENCY CONVERSION CIRCUITS
A processor may calibrate a first actuator electrically coupled to a transconductance stage of the frequency conversion circuit. The transconductance stage may be configured to receive a differential signal input. Calibrating a first actuator may adjust a first basis vector associated with a differential direct current (DC) output of the transconductance stage. A processor may calibrate a second actuator electrically coupled to receive the differential current output of the transconductance stage and electrically coupled to a set of commutating devices of the frequency conversion circuit. The commutating devices may be configured to receive differential LO inputs. Calibrating a second actuator may adjust a second basis vector associated with a differential impedance of the set of commutating devices. A processor may offset responsive to adjusting the first basis vector and the second basis vector, the first leakage basis vector and second leakage basis vector of the LO leakage signal.
Power amplifier and demodulator
A power amplifier includes an in-phase modulator configured to modulate an in-phase component of an input signal, a quadrature modulator configured to modulate a quadrature component of the input signal, and a processor configured to process the in-phase and quadrature components. The processor includes a clock configured to produce a clock signal, a pulse processor configured to remove non-essential information from the modulated in-phase and quadrature components, and a pulse converter configured to select an amplifier class and output a control signal based on the selected amplifier class. A switching network is also included and configured to actuate one or more switches based on the control signal to output an amplified signal.
MIXER
A mixer includes a first unit mixer, a second unit mixer, a third unit mixer, and a fourth unit mixer that have the same configuration and a first combiner, a second combiner, and a third combiner that have the same configuration. The first to the fourth unit mixers each include a differential RF signal terminal. Output of the first unit mixer and output of the second unit mixer are combined by the second combiner. Output of the third unit mixer and output of the fourth unit mixer are combined by the third combiner. Output of the second combiner and output of the third combiner are combined by the first combiner. The output of the third unit mixer is input to the third combiner with the polarity being determined.
Communications device and method for operating a communications device
Embodiments of communications devices and methods for operating a communications device are described. In an embodiment, a communications device includes a complex multiplier configured to multiply a first input complex signal with a second input complex signal to generate an output complex signal, an amplifier configured to amplify an imaginary part of the output complex signal to generate an amplification result, a delay element configured to delay a rotation angle signal that is related to the second input complex signal, and a subtractor configured to subtract the amplification result from the delayed rotation angle signal to generate the rotation angle signal. Other embodiments are also described.
Radio frequency (RF) to digital polar data converter and time-to-digital converter based time domain signal processing receiver
The present disclosure includes a time-to-digital converter (TDC) based RF-to-digital (RDC) data converter for time domain signal processing polar receivers. Polar data conversion achieves better SNR tolerance owing to its phase convergence near the origin in a polar coordinate. The proposed RDC consists of a TDC for phase detection and an analog-to-digital converter (ADC) for amplitude conversion. Unlike the conversional data converter, the proposed ADC's sampling position is guided by the detected phase result from the TDC's output. This TDC assisted data-converter architecture reduces the number of bits required for the ADC. In addition, oversampling is no longer needed. With precisely controlled tunable delay cells and gain compensator, this hybrid data convertor is capable to directly convert Quadrature Amplitude Modulation (QAM) waveforms and Amplitude Phase Shift Keying (APSK) waveforms directly from the RF signal without down-conversion. Thus, the proposed RDC architecture achieves lower power consumption and better performance comparing with conventional I/Q receivers.
Circuits and methods for circulators including a plurality of cancellation paths
A circulator, comprising: a gyrator having a first side (1S) and a second side (2S) connected to a third port; a first transmission line section (TLS) having a 1 S connected to the 1 S of the gyrator and a 2S connected to a first port; a second TLS having a 1S connected to the first port and having a 2S connected to a second port; a third TLS having a 1S connected to the second port and having a 2S connected to the third port; a first cancellation path (CP) that is connected between the first port and the third port and introduces a current that is 90 degrees out of phase with a first voltage at the first port; and a second CP that is connected between the second port and the third port and introduces a current that is orthogonal to the current introduces by the first CP.