Patent classifications
H03F3/505
Cascade complementary source follower and controlling circuit
A cascade complementary source follower and a controlling circuit are provided. The source follower circuit includes: a source follower circuit including at least two MOS transistors, and a feedback circuit configured to clamp a voltage on a MOS transistor that provides an output voltage in the source follower circuit and to change a gate-source voltage of the MOS transistor by adjusting a bias current supplied to the MOS transistor, so that an output voltage can precisely follow an input voltage.
Voltage follower circuit
A voltage follower circuit according to an embodiment includes first and second paths, the first path includes a first nMOS transistor and a first pMOS transistor, the second path includes a second nMOS transistor and a second pMOS transistor, an input voltage is supplied to the gate of the first nMOS transistor, an output voltage is supplied to the gate of the second nMOS transistor, a voltage lower than the output voltage is supplied to the gate of the first pMOS transistor, and a voltage lower than the input voltage is supplied to the gate of the second pMOS transistor.
DIFFERENTIAL AMPLIFIER CIRCUITRY
Differential amplifier circuitry including: first and second main transistors of a given conductivity type; and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.
Analog microphone and control method thereof technical field of the disclosure
An analog microphone and a control method thereof are disclosed. The analog microphone includes a sensor configured to sense an audio signal and convert the audio signal into an electrical signal; a charge pump configured to provide a bias voltage for the sensor to drive the sensor; a source follower configured to receive the electrical signal and convert the electrical signal into a source follower signal; a gain adjustable amplifier configured to receive the source follower signal, multiply the source follower signal by an amplifying factor, and output an amplified signal; and a detecting module configured to adaptively control the bias voltage of the charge pump and the amplified signal of the gain adjustable amplifier in response to the source follower signal of the source follower.
ENVELOPE TRACKING INTEGRATED CIRCUIT OPERABLE ACROSS WIDE MODULATION BANDWIDTH
An envelope tracking (ET) integrated circuit (ETIC) operable across wide modulation bandwidth is disclosed. The ETIC includes at least two auxiliary voltage outputs coupled to a high-bandwidth power amplifier circuit that has a lower equivalent capacitance, and thus a higher impedance resonance frequency. The ETIC also includes a pair of ET voltage circuits configured to generate a pair of ET voltages, respectively. To help mitigate potential distortion in the ET voltages, a control circuit is configured to couple the ET voltage circuits exclusively to the auxiliary voltage outputs when the ETIC needs to operate with a high modulation bandwidth (e.g., 200 MHz). Given the higher impedance resonance frequency of the high-bandwidth power amplifier circuit, it is possible to increase separation between an energy spectrum of a voltage disturbance and an energy spectrum of the high modulation bandwidth, thus helping to reduce the potential distortion in the ET voltages.
SOLID-STATE IMAGING DEVICE AND CLASS AB SUPER SOURCE FOLLOWER
An output buffer of a super source follower for driving a reference ramp signal of a column-parallel single slope type ADC of a solid-state imaging device is made as a class AB feedback configuration for controlling a feedback variable current source with a signal obtained by amplifying a current fluctuation flowing through an amplification transistor by an amplifier, and thereby, the upper limit of the drain voltage of the amplification transistor is not limited by the voltage between the gate and the source of the feedback variable current source.
Signal Coupling Method and Apparatus
A signal coupling method and apparatus is disclosed. A coupling network is coupled to convey signals from first functional circuit block to a second functional circuit block. The coupling network includes a first signal path having a first capacitor for providing AC coupling between the first and second functional circuit blocks. The coupling network further includes a second functional circuit block having a second signal path in parallel with the first signal path. The second signal path includes a switched capacitor circuit coupled to receive a first common mode voltage corresponding to the first functional circuit block and a second common mode voltage corresponding to the second functional circuit block.
IMAGE SENSOR AND OPERATING METHOD THEREOF
An image sensor and an operating method of the image sensor are provided. An image sensor includes a pixel array including a plurality of pixels, a ramp signal generator configured to generate a first ramp signal, a buffer including an amplifier of a super source follower structure and outputting a second ramp signal obtained by buffering the first ramp signal, and an analog-to-digital conversion circuit configured to compare a pixel signal output from the pixel array with the second ramp signal and converting the pixel signal to a pixel value.
Low-voltage high-speed receiver
A line receiver is described. The line receiver may be configured to receive signals transmitted via a communication channel, such as a metal trace on a printed circuit board or a cable. The receiver may comprise a buffer and circuitry for enhancing the trans-conductance gain of the buffer. By enhancing the trans-conductance gain of the buffer, linearity may be improved and susceptibility to process and temperature variations may be limited. Enhancement of the trans-conductance gain may be performed using feedback circuitry coupled to the buffer. The receiver may further comprise mirror circuitry configured to provide a desired current to the load. The receiver may further comprise a gain stage for setting the gain of the receiver to a desired level.
Variable gain amplifier in a receiving chain
A variable gain amplifier includes a pair of amplification and recentering branches. Each branch includes: a resistive element of variable resistance configured to be driven by a variable gain controller; a digitally-driven variable current source configured to be driven by a compensation current driver unit; a first transistor comprising a gate terminal coupled to an input terminal of the variable gain amplifier, and a source terminal coupled to a first terminal of the resistive element; and a second transistor comprising a gate terminal coupled to a drain terminal of the first transistor, and a source terminal coupled to an output terminal of the variable gain amplifier.