A servo-amplifier includes a first bipolar transistor, a second bipolar transistor, a cascode transistor, and a bias transistor. The second bipolar transistor includes an emitter terminal that is connected to an emitter terminal of the first bipolar transistor to form a differential amplifier. The cascode transistor includes a source terminal that is connected to a collector terminal of the first bipolar transistor. The bias transistor is coupled to the first bipolar transistor, the second bipolar transistor and the cascode transistor. The bias transistor is configured to generate a bias voltage to drive a gate terminal of the cascode transistor based on a voltage at a base terminal of the first bipolar transistor and a voltage at a base terminal of the second bipolar transistor. As a result, neither of the bipolar transistors enters a saturation region during transient or steady state operation.

An amplifier including a signal input terminal, at least one signal output terminal, a first and a second cascode amplifier circuits, a capacitor and a loading circuit. The signal input terminal receives an input signal. The first cascode amplifier circuit includes a first and a second input terminals and a first and a second output terminals. The first input terminal coupled to the signal input terminal receives the input signal. The second cascode amplifier circuit includes a third and a fourth input terminals and a third output terminal. The third input terminal is coupled to the first output terminal, and the third output terminal is coupled to the second input terminal. Two terminals of the capacitor are coupled to the fourth input terminal and the first output terminal respectively. A terminal of the loading circuit is coupled to the third output terminal, and another terminal of the loading circuit is coupled to the second output terminal. At least one of two terminals of the loading circuit is further coupled to the at least one signal output terminal.

An amplifier includes a differential input stage, a hysteresis stage, coupled to the differential input stage, a cascode stage coupled to the hysteresis stage, a feedback stage coupled to an output of the cascode stage and configured to provide a feedback signal to the hysteresis stage, and an output stage coupled to the output of the cascode stage. The output stage includes a hysteresis inverter coupled between the output of the cascode stage and the amplifier output.

An amplifier includes a differential input stage, a hysteresis stage, coupled to the differential input stage, a cascode stage coupled to the hysteresis stage, a feedback stage coupled to an output of the cascode stage and configured to provide a feedback signal to the hysteresis stage, and an output stage coupled to the output of the cascode stage. The output stage includes a hysteresis inverter coupled between the output of the cascode stage and the amplifier output.

An amplifier for a receiver circuit is disclosed. The amplifier has an input node (V.sub.in) and an output node (V.sub.out). It comprises a tunable tank circuit connected to the output node (V.sub.out), a feedback circuit path connected between the output node (V.sub.out) and the input node (V.sub.in), and a tunable capacitor connected between an internal node of the feedback circuit path and a reference-voltage node. A receiver circuit and a communication apparatus is disclosed as well.

A method operates to bias an RF receiver by incorporating a first NMOSFET as a common-source amplifier; incorporating a second NMOSFET as a cascode device stacked upon the first NMOSFET, injecting a reference current into a drain of a third NMOSFET; using a first operational amplifier to generate a first bias voltage to control a gate of the first NMOSFET, a gate of the third NMOSFET, and a gate of a fourth NMOSFET in accordance with a voltage difference between the drain of the third NMOSFET and a drain of the fourth NMOSFET; incorporating a fifth NMOSFET stacked upon the fourth NMOSFET; and using a second operational amplifier to generate a second bias voltage to control a gate of the second NMOSFET and a gate of the fifth NMOSFET in accordance with a voltage difference between a reference voltage and the drain of the fourth NMOSFET.

An apparatus includes a differential cascode amplifier including a first transistor and a second transistor. The apparatus further includes a transistor including a source terminal coupled to a gate terminal of the first transistor of the differential cascode amplifier. The transistor also includes a drain terminal coupled to a gate terminal of the second transistor of the differential amplifier.

A differential amplifier comprises a first differential circuitry structure including a first part comprising at least one branch of transistors and a second part comprising at least one branch of transistors, and a second circuitry structure. The second circuitry structure has a first non-linear device and a second non-linear device. The non-linear devices each comprise a transistor having a control node connected to a differential output terminals of the differential amplifier. A common center node of the non-linear devices is connected to a control node of one of the transistors of each branch of the first part having a differential output terminal. Amplifier applications, communication devices and network nodes are also disclosed.

An amplifier for a receiver circuit is disclosed. The amplifier has an input node (V.sub.in) and an output node (V.sub.out). It comprises a tunable tank circuit connected to the output node (V.sub.out), a feedback circuit path connected between the output node (V.sub.out) and the input node (V.sub.in), and a tunable capacitor connected between an internal node of the feedback circuit path and a reference-voltage node. A receiver circuit and a communication apparatus is disclosed as well.

An amplifier includes an input stage. The input stage includes a differential pair and a load circuit. The differential pair includes a first transistor and a second transistor. The first transistor and the second transistor are configured to amplify a received differential signal. The load circuit connects the differential pair to a reference voltage. The load circuit is configured to vary in resistance in inverse proportion to the transconductance of the first transistor and the second transistor.