A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.

An amplifier circuit can be configured to receive a differential input signal having a common mode component that can extend to at least one power supply rail for the amplifier circuit. The amplifier circuit can include an input stage, such as having a first differential transistor pair, and the input stage can receive the differential input signal and in response conduct a differential first current to a cascode output stage. The cascode output stage can include or use a cascode control signal that is adjusted in response to the differential input signal. The cascode control signal can be independent of a transconductance of the first differential transistor pair. In an example, the amplifier circuit includes a slew boost circuit configured to source or sink current at an output of the amplifier based on a magnitude and polarity of the differential input signal.

Transimpedance amplifiers with feedforward current are provided herein. In certain embodiments, an amplifier system includes a transimpedance amplifier that amplifies an input current received at an input to generate an output voltage at an output. The amplifier system further includes a controllable current source that is coupled to the output of the transimpedance amplifier, and operable to provide a feedforward current that changes in relation to the input current of the transimpedance amplifier. By providing a feedforward current in this manner, gain and speed performance of the transimpedance amplifier is enhanced.

A power supply in a test and measurement device includes a stimulus having an output coupled to an amplifier in which an output signal from the stimulus controls an output level of the amplifier. The stimulus may include a Digital to Analog Converter. A measurement circuit detects the output level of the amplifier. The power supply includes an overpulse generator that can be structured to accept a desired amplifier output level, overdrive the stimulus at a first level for a first time period, and drive the stimulus at a second level for a second time period. The measurement circuit determines when the overpulse generator switches from driving the stimulus at the first level to driving the stimulus at the second level. The time period for driving the stimulus at the second level starts as the actual amplifier output level approaches the desired amplifier output level.

A differential amplifier generates an output voltage waveform exhibiting a slew rate over a rise time. The amplifier is powered from a dc voltage input and includes a set of differential pairs having a bias current flowing therethrough and a Miller compensation capacitance. A comparator functions to compare a voltage at the dc voltage input against a reference voltage in order to detect when the voltage drops below the reference voltage. A gain stage controls the gain of the differential amplifier and a bias current control circuit controls the bias current of the differential amplifier. In response to the detection by the comparator of the voltage dropping below the reference voltage, the gain stage and the bias current control circuit decrease the gain of the amplifier and jointly decrease the bias current in order to maintain a value of the rise time.

A voltage follower circuit according to an embodiment includes first and second paths, the first path includes a first nMOS transistor and a first pMOS transistor, the second path includes a second nMOS transistor and a second pMOS transistor, an input voltage is supplied to the gate of the first nMOS transistor, an output voltage is supplied to the gate of the second nMOS transistor, a voltage lower than the output voltage is supplied to the gate of the first pMOS transistor, and a voltage lower than the input voltage is supplied to the gate of the second pMOS transistor.

A slew rate adjusting circuit includes an adjustment transistor configured to provide an adjustment current into an output port of an arithmetic amplifier, a first transistor connected between a power line of the arithmetic amplifier and the adjustment transistor, and a second transistor connected between the first transistor and an output node of the output port, wherein the adjustment transistor is turned on by the second transistor in response to a difference between an input voltage and an output voltage being equal to or greater than a reference voltage, and the adjustment current is provided to the output port in response to the adjustment transistor being turned on.

The techniques described herein relate to a circuit including an operational amplifier that includes a differential amplifier, a capacitor, and an output stage. The differential amplifier includes a first input and a second input. The output stage is configured to generate an output voltage. The circuit includes a slew-rate boost circuitry connected to the operational amplifier. The slew-rate boost circuitry is configured to detect a voltage differential between the first input and the second input and apply, at an output of the differential amplifier, a boost current to charge the capacitor during a period of time in which the output voltage increases or decreases to a target voltage level.

Disclosed is an amplifier capable of minimizing shortcircuit current of an output stage of a buffer upon transition of an output voltage while having a high slew rate without increasing power consumption. The amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, and a short-circuit current minimization circuit. Alternatively, the amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, a short-circuit current minimization circuit, and a slew rate improvement circuit.

A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.