An example log power detector includes a gain or attenuation circuit and a detector circuit. The gain or attenuation circuit includes a plurality of gain or attenuation elements arranged in a sequence, each gain or attenuation element configured to generate an output signal that is an amplified or attenuated version of an input signal provided thereto. The detector circuit includes a plurality of detectors, each detector configured to receive the output signal from a different one of the gain or attenuation elements and to generate a signal indicative of a power of the received output signal. At least the last detector is configured to receive a DC offset signal that is different from a DC offset signal received by at least one other detector. Such a log detector may provide effective noise compensation to reduce errors caused by input noise, especially for low-power and/or high-frequency input signals.

An adaptive continuous-time linear equalizer (CTLE) includes a CTLE cell including input terminals and output terminals, a low-pass filter configured to respectively output low-band differential signals obtained by respectively low-pass filtering differential output signals, and an error amplifier configured to amplify a difference between the low-band differential signals and output the difference as a control voltage. The CTLE cell includes first and second transistors each including an input terminal and an output terminal and an offset compensator configured to adjust a potential difference between a supply voltage source and the output terminal according to the control voltage.

Embodiments presented herein provide apparatus and techniques to reduce a direct current (DC) voltage offset between a transmitter and receiver. Embodiments include a shared reference voltage signal generated by a reference voltage source. The receiver may include a first unit gain buffer to receive a reference voltage signal from the reference voltage source. The transmitter may be communicatively coupled to the receiver via one or more connections and may include a second unit gain buffer communicatively coupled to the first unit gain buffer via one of the connections. An amplifier (e.g., an operation amplifier) of the transmitter may include multiple positive inputs coupled to the second unit gain buffer and an offset tracker. The offset tracker may compensate for a DC offset caused by at least a power supply and/or a ground bounce.

Embodiments presented herein provide apparatus and techniques to reduce a direct current (DC) voltage offset between a transmitter and receiver. Embodiments include a shared reference voltage signal generated by a reference voltage source. The receiver may include a first unit gain buffer to receive a reference voltage signal from the reference voltage source. The transmitter may be communicatively coupled to the receiver via one or more connections and may include a second unit gain buffer communicatively coupled to the first unit gain buffer via one of the connections. An amplifier (e.g., an operation amplifier) of the transmitter may include multiple positive inputs coupled to the second unit gain buffer and an offset tracker. The offset tracker may compensate for a DC offset caused by at least a power supply and/or a ground bounce.

An example apparatus includes: a first voltage source, a first amplifier having a noninverting input adapted to be coupled to a photodiode anode and coupled to the first voltage source, an inverting input adapted to be coupled to a photodiode cathode, and an output, a first resistor coupled to the first amplifier inverting input and to the first amplifier output, a first capacitor coupled to the inverting input of the first amplifier and the first amplifier output, and a second voltage source different from the first voltage source. There is a second amplifier having a noninverting input, an inverting input and an output. The noninverting input is coupled to the output of the first amplifier, the inverting input is coupled to the second voltage source, and there is a second resistor coupled to the inverting input and the output of the second amplifier.

The present invention relates to a sensing circuit with signal compensation, which comprises a first sensing element, a second sensing element and a differential amplifying circuit, the differential amplifying circuit generates an output signal through a differential compensation according to a common mode voltage, a first sensing signal and a second sensing signal. Hereby, reducing the noise of the sensing circuit is achieved, and the interference of the display driving signal may be effectively improved.

An offset-cancellation circuit having a first amplification stage with a gain of the first amplification stage and configured to receive an offset voltage of a first amplifier. A storage element is configured to be coupled to and decoupled from the first amplification stage and configured to store a potential difference output by the first amplification stage. The potential difference is determined by the offset voltage of the first amplifier and the gain of the first amplification stage. A second amplification stage is coupled to the storage element and configured to receive the potential difference from the storage element when the storage element is decoupled from the first amplification stage and configured to deliver an offset-cancellation current. The offset-cancellation current is determined by the potential difference and a gain of the second amplification stage.

An offset compensated differential amplifier employing a multi-tan h circuit comprising differential pairs coupled in parallel to compensate for an offset voltage of the output voltage in the offset compensation calibration mode is disclosed. The differential pairs each include a compensation transistor coupled to the positive internal node and a reference transistor coupled to the negative internal node. Each compensation transistor receives the compensation control voltage and each reference transistor receives a different reference voltage. The multi-tan h circuit generates an offset compensation voltage on the positive and negative internal nodes based on a difference between the compensation control voltage and the different reference voltages. The multi-tan h circuit comprises a larger linear range than a hyperbolic tangent current transfer function of a single differential pair. The offset compensated differential amplifier provides offset compensation with improved linearity and a finer granularity compared to a conventional differential amplifier.

An offset-cancellation circuit having a first amplification stage with a gain of the first amplification stage and configured to receive an offset voltage of a first amplifier. A storage element is configured to be coupled to and decoupled from the first amplification stage and configured to store a potential difference output by the first amplification stage. The potential difference is determined by the offset voltage of the first amplifier and the gain of the first amplification stage. A second amplification stage is coupled to the storage element and configured to receive the potential difference from the storage element when the storage element is decoupled from the first amplification stage and configured to deliver an offset-cancellation current. The offset-cancellation current is determined by the potential difference and a gain of the second amplification stage.

A circuit arrangement comprises a first input node, a first output node, a sampling capacitor means and a first switching means being switchable between a first switching state and a second switching state. The first switching means is coupled to the sampling capacitor means, the first input node and the first output node in such a way that the sampling capacitor means is conductively connected to the first input node and disconnected from the first output node in the first switching state and the sampling capacitor means is disconnected from the first input node and conductively connected to the first output node in the second switching state. A first charge-storing element is coupled via a second switching means to the first input node in such a way that the charge-storing element is charged in the first switching state and discharged in the second switching state, thereby at least partly compensating current flow for charging the sampling capacitor means in the first switching state.