Methods and apparatuses for signal attenuation is described. In an example, an attenuator can be configured to perform attenuation of signals for an integrated circuit. The attenuator can vary the attenuation with an ambient temperature. The attenuator can further adjust the attenuation based on a control signal applied to the attenuator. The control signal can be based on one or more of a temperature profile of the attenuator and a target gain variation of the integrated circuit.

A method for improving the stability and reducing phase variations of an ultra-wideband attenuator, with respect to temperature variations, comprising the steps of providing an attenuator implemented in π-topology and consisting of a serial path between the input and the output of the attenuator, including a first serial resistor Rs.sub.1 connected to the input, followed by a serial inductor Ls, followed by a second serial resistor Rs.sub.2 connected to the output; a first transistor T.sub.1 bridging between the input and the output, for controlling the impedance of the serial path by a first control input provided to the first transistor T.sub.1; a first parallel path between the input and ground, including a first parallel transistor T.sub.2a followed by first parallel resistor Rp.sub.1; a second parallel path between the output and ground, including a second parallel transistor T.sub.2b followed by second parallel resistor Rp.sub.2; a second control input commonly provided to first parallel transistor T.sub.2a and to the second parallel transistor T.sub.2b, for controlling the impedance of the first and second parallel paths; unifying the serial resistors to a common serial resistor Rs and splitting the serial inductor Ls to two serial inductors Ls.sub.1 and Ls.sub.2, such that one serial inductor is connected between the input and a first contract of the common serial resistor Rs and the other serial inductor is connected between the output and the other contact of the common serial resistor Rs; splitting the parallel resistor Rp.sub.1 to two smaller resistors, connecting a first smaller resistor to the input, connecting a second smaller resistor to the first smaller resistor via the first parallel transistor T.sub.2a and to ground via a third parallel transistor T.sub.3a; splitting the parallel resistor Rp.sub.2 to two smaller resistors, connecting a third smaller resistor to the output, connecting a fourth smaller resistor to the third smaller resistor via the second parallel transistor T.sub.2b and to ground via a fourth parallel transistor T.sub.3b; connecting a first feedback capacitor Cfb.sub.1 between the common point connecting between the ungrounded port of the second parallel transistor T.sub.3a and the first contract of the common serial resistor Rs and connecting a second feedback capacitor Cfb.sub.2 between the common point connecting between the ungrounded port of the fourth parallel transistor T.sub.3b and the second contract of the common serial resistor Rs; upon controlling the first and second parallel transistors T.sub.2a and T.sub.2b by the second control input, simultaneously controlling also the third and the fourth parallel tran

A digital step attenuator (DSA) cell and related method are provided. The DSA cell includes a first branch comprising a first resistor connected, at a first side, to an input port and, at a second side, to an output port; a second resistor connected, at a first side, to the first resistor and, at a second side, to a first transistor and a third resistor connected, at a first side, to the first resistor and, at a second side, to a second transistor. Also included in the DSA cell is a second branch, in a parallel configuration with the first resistor, that includes a fourth resistor and a third transistor. Also included is a third branch, in a parallel configuration with the first resistor, that includes a fourth transistor. The first transistor, the second transistor, the third transistor, and the fourth transistor are configured to be operated independently.

An ultrasound device, including a profile generator, an encoder configured to receive a profile signal from the profile generator, and an attenuator configured to receive a signal representing an output of an ultrasound sensor and coupled to the encoder to receive a control signal from the encoder, the attenuator including a plurality of attenuator stages, the attenuator configured to produce an output signal that is an attenuated version of the input signal.

A power switch including input and output lines of characteristic impedance Z0, and a switching area connected serially between the input and output lines, the switching area being formed by N (integer >2) parallel conducting branchesand i belonging to {1, . . . , N}, each conducting branch having, from input to output lines of the switch, an input line portion with characteristic impedance Zbei in series with a switching circuit in series with an output line portion with characteristic impedance Zbsi, the switching circuit configured, in a first state, to block passage of a signal between the input and output line portions of the conducting branch and, in a second state, to transmit a signal between the input line portion and the output line portion of the conducting branch with a maximum reflection coefficient of 0.316, each of the characteristic impedances Zbei and Zbsi ranging from 0.75*N*Z0 to 1.35*N*Z0.

The application provides an attenuator and a differential voltage probe, comprising a forward attenuation circuit and a reverse attenuation circuit which are symmetrical with each other, a first compensation unit and a third compensation unit which are symmetrical with each other, a second compensation unit and a fourth compensation unit which are symmetrical with each other, and a differential amplifier; the four compensation units are all adjustable capacitor units composed of constant capacitance; a positive-going signal to be tested is attenuated by the forward attenuation circuit, and frequency characteristics of a preset frequency point are adjusted by the first compensation unit and second compensation unit; a negative-going signal to be tested is attenuated by the reverse attenuation circuit, and frequency characteristics of a preset frequency point are adjusted by the third compensation unit and fourth compensation unit; finally, the difference value is calculated by the differential amplifier, amplified and output.

A digital step attenuator (DSA) cell and related method are provided. The DSA cell includes a first branch comprising a first resistor connected, at a first side, to an input port and, at a second side, to an output port; a second resistor connected, at a first side, to the first resistor and, at a second side, to a first transistor and a third resistor connected, at a first side, to the first resistor and, at a second side, to a second transistor. Also included in the DSA cell is a second branch, in a parallel configuration with the first resistor, that includes a fourth resistor and a third transistor. Also included is a third branch, in a parallel configuration with the first resistor, that includes a fourth transistor. The first transistor, the second transistor, the third transistor, and the fourth transistor are configured to be operated independently.

A single pole double throw (SPDT) switch with embedded attenuators includes a transmitter attenuator circuit directly connected to a common input of the SPDT switch, and a receiver attenuator circuit directly connected to the common input of the SPDT switch. Switches in the transmitter attenuator circuit and in the receiver attenuator circuit are selectively or individually set to an open state or to a closed state to directly connect the transmitter attenuator circuit or the receiver attenuator circuit to the common input. The selective setting of the states of the switches also determines a given amount of attenuation for the transmitter attenuator circuit or the receiver attenuator circuit.

A low noise amplifier for an RF sampling analog front end. The amplifier includes digital step attenuation for applying a selected attenuation to signals received at an input node, and a gain stage coupled to amplify the attenuated signal from the digital step attenuation circuit. In a differential amplifier implementation, a first input capacitor is coupled between a positive side input node and an output of the negative side digital attenuation circuit, and a second input capacitor is coupled between a negative side input node and an output of the positive side digital step attenuation circuit. In some embodiments, variable feedback circuits are coupled between each input node and an output of the corresponding gain stage, to selectively apply active termination at the input at high gain settings of the amplifier. Variable input and output resistors, and programmable noise filtering at the output, are provided in some embodiments.

Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2.sup.n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.