Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2.sup.n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.

A method for improving the stability and reducing phase variations of an ultra-wideband attenuator, with respect to temperature variations, comprising the steps of providing an attenuator implemented in π-topology and consisting of a serial path between the input and the output of the attenuator, including a first serial resistor Rs.sub.1 connected to the input, followed by a serial inductor Ls, followed by a second serial resistor Rs.sub.2 connected to the output; a first transistor T.sub.1 bridging between the input and the output, for controlling the impedance of the serial path by a first control input provided to the first transistor T.sub.1; a first parallel path between the input and ground, including a first parallel transistor T.sub.2a followed by first parallel resistor Rp.sub.1; a second parallel path between the output and ground, including a second parallel transistor T.sub.2b followed by second parallel resistor Rp.sub.2; a second control input commonly provided to first parallel transistor T.sub.2a and to the second parallel transistor T.sub.2b, for controlling the impedance of the first and second parallel paths; unifying the serial resistors to a common serial resistor Rs and splitting the serial inductor Ls to two serial inductors Ls.sub.1 and Ls.sub.2, such that one serial inductor is connected between the input and a first contract of the common serial resistor Rs and the other serial inductor is connected between the output and the other contact of the common serial resistor Rs; splitting the parallel resistor Rp.sub.1 to two smaller resistors, connecting a first smaller resistor to the input, connecting a second smaller resistor to the first smaller resistor via the first parallel transistor T.sub.2a and to ground via a third parallel transistor T.sub.3a; splitting the parallel resistor Rp.sub.2 to two smaller resistors, connecting a third smaller resistor to the output, connecting a fourth smaller resistor to the third smaller resistor via the second parallel transistor T.sub.2b and to ground via a fourth parallel transistor T.sub.3b; connecting a first feedback capacitor Cfb.sub.1 between the common point connecting between the ungrounded port of the second parallel transistor T.sub.3a and the first contract of the common serial resistor Rs and connecting a second feedback capacitor Cfb.sub.2 between the common point connecting between the ungrounded port of the fourth parallel transistor T.sub.3b and the second contract of the common serial resistor Rs; upon controlling the first and second parallel transistors T.sub.2a and T.sub.2b by the second control input, simultaneously controlling also the third and the fourth parallel tran

A digital step attenuator (DSA) cell and related method are provided. The DSA cell includes a first branch comprising a first resistor connected, at a first side, to an input port and, at a second side, to an output port; a second resistor connected, at a first side, to the first resistor and, at a second side, to a first transistor and a third resistor connected, at a first side, to the first resistor and, at a second side, to a second transistor. Also included in the DSA cell is a second branch, in a parallel configuration with the first resistor, that includes a fourth resistor and a third transistor. Also included is a third branch, in a parallel configuration with the first resistor, that includes a fourth transistor. The first transistor, the second transistor, the third transistor, and the fourth transistor are configured to be operated independently.

A resonator device includes a substrate with a first number of fins extending over the substrate. The fins extend along the substrate in a first direction. A second number of conductive fingers are provided over the fins, which extend in a second direction perpendicular to the first direction. The first number is less than or equal to the second number. The conductive fingers are configured to receive an input signal such that the conductive fingers resonate at an output frequency. The conductive fingers define a finger pitch therebetween, and the output frequency is based on the finger pitch.

A digital step attenuator (DSA) cell and related method are provided. The DSA cell includes a first branch comprising a first resistor connected, at a first side, to an input port and, at a second side, to an output port; a second resistor connected, at a first side, to the first resistor and, at a second side, to a first transistor and a third resistor connected, at a first side, to the first resistor and, at a second side, to a second transistor. Also included in the DSA cell is a second branch, in a parallel configuration with the first resistor, that includes a fourth resistor and a third transistor. Also included is a third branch, in a parallel configuration with the first resistor, that includes a fourth transistor. The first transistor, the second transistor, the third transistor, and the fourth transistor are configured to be operated independently.

A single pole double throw (SPDT) switch with embedded attenuators includes a transmitter attenuator circuit directly connected to a common input of the SPDT switch, and a receiver attenuator circuit directly connected to the common input of the SPDT switch. Switches in the transmitter attenuator circuit and in the receiver attenuator circuit are selectively or individually set to an open state or to a closed state to directly connect the transmitter attenuator circuit or the receiver attenuator circuit to the common input. The selective setting of the states of the switches also determines a given amount of attenuation for the transmitter attenuator circuit or the receiver attenuator circuit.

An active filter reduces Electro-Magnetic Interference (EMI) created by current flowing through a power line. The active filter connects to the power line at a single node through a connection capacitor. A sense current flows through the connection capacitor when the power line current changes. This sense current is applied to a gain control circuit having cross-coupled PNP transistors that drive currents to both terminals of a variable capacitor. The variable capacitor converts these currents to a voltage that is injected back into the power line through the connection capacitor as an injected compensation voltage that compensates for the sensed current.

A signal generation unit 2, a DA converter 3, variable attenuators 40, 42, 44, and 46 that attenuate the analog signal converted by the DA converter 3, a measurement unit 6 that detects a level of the signal attenuated by the variable attenuators 40, 42, 44, and 46 and passed through one or more semiconductor components, and a control unit 7 that obtains a value of a step error, which is a correction value of an attenuation amount of the variable attenuators 40, 42, 44, and 46 in each of a plurality of steps obtained by dividing a maximum value of the attenuation amount of the variable attenuators 40, 42, 44, and 46 by a variation amount, which is a predetermined attenuation amount are included.

A signal generation unit 2, a DA converter 3, variable attenuators 40, 42, 44, and 46 that attenuate the analog signal converted by the DA converter 3, a measurement unit 6 that detects a level of the signal attenuated by the variable attenuators 40, 42, 44, and 46 and passed through one or more semiconductor components, and a control unit 7 that obtains a value of a step error, which is a correction value of an attenuation amount of the variable attenuators 40, 42, 44, and 46 in each of a plurality of steps obtained by dividing a maximum value of the attenuation amount of the variable attenuators 40, 42, 44, and 46 by a variation amount, which is a predetermined attenuation amount are included.

Monolithic attenuator, limiter, and linearizer circuitry to be integrated with other circuitry on a chip are provided. According to one aspect, a monolithic attenuator and limiter circuit comprises an input terminal, an output terminal, a first resistor having a first terminal coupled to the input terminal and a second terminal coupled to the output terminal, and a second resistor having a first terminal coupled to the first or second terminal of the first resistor and a second terminal coupled to ground. At least the first resistor is a non-linear resistor whose resistance changes as a function of the voltage across the resistor. The monolithic attenuator and limiter circuit may be part of a “Pi” or “Tee” topology. According to another aspect, a non-linear shunt resistor coupled to the input of an amplifier circuit can operate to linearize the gain of the amplifier circuit over a range of input levels.