The present invention relates an implantable pulse generator comprising an electric circuit, wherein the electric circuit comprises: a primary energy store, at least one secondary energy store, and a control unit, wherein the control unit is configured to activate an electric switch in the electric circuit in such a way that, in a first interval of a first phase of a pulse delivery, the primary energy store is discharged via a therapeutic current path, and to activate an electric switch in the electric circuit in such a way that, in a second interval of the first phase of the pulse delivery, the secondary energy store is discharged via the therapeutic current path, wherein the primary energy store and the at least one secondary energy store are fixedly connected, or connectable, in series, and wherein the implantable pulse generator is designed to deliver a shock having an approximately rectangular pulse waveform.

According to one embodiment, a drive control circuit includes a first transistor that supplies a current to a gate of an output transistor in response to a drive signal, a second transistor that supplies a current to a capacitor in response to the drive signal, a comparison circuit that compares a gate voltage of the output transistor and a voltage of the capacitor, a control signal generation circuit that generates a control signal in response to an output signal of the comparison circuit and the drive signal, and a third transistor that supplies a current to a gate of the output transistor in response to the control signal.

According to one embodiment, a drive control circuit includes a first transistor that supplies a current to a gate of an output transistor in response to a drive signal, a second transistor that supplies a current to a capacitor in response to the drive signal, a comparison circuit that compares a gate voltage of the output transistor and a voltage of the capacitor, a control signal generation circuit that generates a control signal in response to an output signal of the comparison circuit and the drive signal, and a third transistor that supplies a current to a gate of the output transistor in response to the control signal.

An electric circuit for generating a pulse width modulated output signal is provided. The electric circuit includes at least one power supply signal input and a first circuitry configured to generate and output an intermediate signal based on the power supply signal input. Further, the electric circuit includes a second circuitry configured to generate the pulse width modulated output signal based on the intermediate signal. The second circuitry includes an energy storage element and a charging/discharging circuitry configured to charge and discharge the energy storage element using the intermediate signal to modify an energy state of the energy storage element. The second circuitry is configured to generate the pulse width modulated output signal based on the energy state of the energy storage element.

An optical emission circuit includes a power supply source and a regulation circuit coupled to control the power supply source. An optical source and a first switch are coupled in series to the power supply source. A square pulse signal source has an output coupled to a control input of the first switch. The square pulse signal source is configured to provide a square pulse signal. The regulation circuit regulates the current supplied by the power supply source according to a product of a peak current set point by a duty cycle of the square pulse signal.

An optical emission circuit includes a power supply source and a regulation circuit coupled to control the power supply source. An optical source and a first switch are coupled in series to the power supply source. A square pulse signal source has an output coupled to a control input of the first switch. The square pulse signal source is configured to provide a square pulse signal. The regulation circuit regulates the current supplied by the power supply source according to a product of a peak current set point by a duty cycle of the square pulse signal.

An implantable pulse generator comprises a pulse generation device generating an output pulse, the pulse generation device comprising a control unit, shock generation circuitry and output circuitry. The shock generation circuitry comprises a first energy storage device, a second energy storage device and a switching device. The switching device is electrically connected to the first energy storage device, and is configured to connect, in a closed state, the first energy storage device with the second energy storage device, and to disconnect, in an open state, the first energy storage device from the second energy storage device. The shock generation circuitry configured to generate an output pulse by supplying energy to the output circuitry, in the open state, from the first energy storage device via a first connection line and, in the closed state, from the first energy storage device and the second energy storage device via a second connection line.

The present disclosure includes circuits and methods that adjust and correct duty cycles of circuits. The circuits and methods receive a signal from a first circuit and forward the received signal to a second circuit that retrieves a first setting (X) that provides a measure of duty cycle of the received signal. The circuits and methods then invert the received signal, retrain the second circuit based upon the inverted received signal, and retrieve a second setting (Y) of the retrained second circuit. The second setting (Y) provides a measure of duty cycle of the inverted received signal. The circuits and methods then adjust the duty cycle of the received signal based upon the first and second settings (X, Y) and further retrain of the second circuit to provide an improved duty cycle in a direction closer to 50 percent.

A bandgap reference circuit and method of using the same are provided. The bandgap reference circuit includes a startup component; an output component; and a bandgap core component coupled there-between. The bandgap core component includes a reference point having a voltage associated with an output signal of the output component. A controller is configured for controlling the bandgap core component and the output component to switch between a low power consumption mode and a normal operation mode based on the voltage at the reference point. When the bandgap core component and the output component operate in the normal operation mode, the bandgap reference circuit outputs a stable voltage and has a first power consumption. When the bandgap core component and the output component operate in the low power consumption mode, the bandgap reference circuit has a second power consumption less than the first power consumption.

A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit.