[Problem]

To provide a signal generation apparatus that is used in a ToF camera system especially adopting an indirect system and can suppress occurrence of erroneous distance measurement caused by distance measurement of a same target by a plurality of cameras with a simple configuration.

[Solving means]

There is provided a signal generation apparatus including a first pulse generator configured to generate a pulse to be supplied to a light source that irradiates light upon a distance measurement target, a second pulse generator configured to generate a pulse to be supplied to a pixel that receives the light reflected by the distance measurement target, and a signal generation section configured to generate a pseudo-random signal for inverting a phase of signals to be generated by the first pulse generator and the second pulse generator.

Edge combiners with symmetrical operation range at high speed are provided. In certain embodiments, an edge combiner (80) includes a circuit state element (71) having a first input controlled by a first timing signal (SI), and a pulse generator (72) that resets the circuit state element by controlling a second input (R) of the circuit state element based on a second timing signal (S2). The edge combiner further includes a first delay circuit (75), and an output logic gate (77) having a first input connected to a data output (Q) of the circuit state element through a first signal path that bypasses the first delay circuit (75), a second input (QD) connected to the data output through a second signal path that includes the first delay circuit, and an output (OUT) that provides an output signal indicating delay between an edge of the first timing signal and an edge of the second timing signal.

Edge combiners with symmetrical operation range at high speed are provided. In certain embodiments, an edge combiner (80) includes a circuit state element (71) having a first input controlled by a first timing signal (SI), and a pulse generator (72) that resets the circuit state element by controlling a second input (R) of the circuit state element based on a second timing signal (S2). The edge combiner further includes a first delay circuit (75), and an output logic gate (77) having a first input connected to a data output (Q) of the circuit state element through a first signal path that bypasses the first delay circuit (75), a second input (QD) connected to the data output through a second signal path that includes the first delay circuit, and an output (OUT) that provides an output signal indicating delay between an edge of the first timing signal and an edge of the second timing signal.

This application relates to methods and apparatus for controlling slew-rate of components for outputting an analogue output signal. Described is a signal processing circuit having a forward signal path for receiving an input signal and outputting an analogue output signal. The signal processing circuit has a first component located in said forward signal path for outputting the analogue output signal. A predictor is configured to predict a required slew-rate for the first component based on the input signal and a controller is configured to controllably vary an output slew-rate limit of the first component based on the prediction of required slew-rate.

This application relates to methods and apparatus for controlling slew-rate of components for outputting an analogue output signal. Described is a signal processing circuit having a forward signal path for receiving an input signal and outputting an analogue output signal. The signal processing circuit has a first component located in said forward signal path for outputting the analogue output signal. A predictor is configured to predict a required slew-rate for the first component based on the input signal and a controller is configured to controllably vary an output slew-rate limit of the first component based on the prediction of required slew-rate.

A laser driver includes a pulse generator circuit, a pulse scaling circuit, and a power stage circuit. The pulse generator circuit generates a first voltage pulse of a first duration. The pulse scaling circuit includes a first transistor with a first gate electrode receiving the first voltage pulse, a capacitor having an electrode connected to a common terminal of a pair of resistors connected in series with the first transistor, and a second transistor with a second gate electrode connected to the first gate electrode and a second drain electrode coupled to a supply voltage via a resistor. Responsive to the reception of the first voltage pulse, a second voltage pulse of a second duration shorter than the first duration is generated at the second drain electrode. The power stage circuit converts the second voltage pulse into a current pulse driving at least one emission element of a laser display.

A pulse stretcher is disclosed comprising, a stretcher input (10) and a stretcher output (20); an asynchronous finite state machine; and a delay generator (40) having a delay input connected to the stretcher output, and a delay output connected to a second input of the FSM. The asynchronous FSM comprises: a first Muller C-element gate (250) having an output connected to the stretcher output, a second Muller C-element gate (260) having an output; and a combinatorial logic circuit (270) connected to the stretcher input, to first and second inputs of each of the first and second C-elements. The first and second Muller C-element gates are cross-coupled via the combinatorial logic, such that the respective outputs of the C-element gates are complementary and, in response to receiving the input pulse at the stretcher input, the output of the first Muller C-element gate provides a stretched version of the input pulse.

A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.

A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.

A comparator circuit includes a first comparator configured to compare a voltage based on an input voltage with a first reference voltage, a charge/discharge portion configured to switch between charging and discharging of a capacitor based on an output of the first comparator, a second comparator configured to compare a voltage of the capacitor with a second reference voltage, and a control portion. The control portion is configured to, in a case where the voltage of the capacitor is larger than a predetermined value when the charge/discharge portion performs switching from the charging of the capacitor to the discharging thereof, supply a predetermined voltage instead of the voltage based on the input voltage to the first comparator until the voltage of the capacitor becomes smaller than the predetermined value so that the discharging of the capacitor is maintained by the charge/discharge portion.